The aggressive downscaling of FET devices (FinFET, NanowireFET, NanosheetFET, to name a few) in past years has put a great emphasis on the need to come up with properly calibrated process and device simulation tools to predict performances, suggest processing options and even understand failure mechanisms. As their modeling is complex with multiple calibration parameters, adequate two- and three-dimensional characterization techniques have been identified as a necessity to achieve an accurate modeling and calibration of the complex physical mechanisms for scaled devices. In such scaled devices even the smallest variations of the structure dimensions (i.e., width or length, local interconnect or spacer, source/drain epi volumes, etc.), carrier distribution and/or activation rate can cause significant variations in the electrical properties.