In a digital VCR, the DCT/IDCT is performed by both the 8/spl times/8 mode and the 2/spl times/4/spl times/8 mode to improve the coding efficiency. A new 2-D DCT/IDCT processor which requires minimal hardware overhead for 8/spl times/8/2/spl times/4/spl times/8 mode change for a digital VCR is presented. The proposed DCT/TDCT processor uses a concurrent architecture and executes both the DCT and IDCT with 8/spl times/8 and 2/spl times/4/spl times/8 mode selection. This chip is implemented on the basis of the row-column decomposition scheme. The proposed architecture minimizes the hardware overhead for the 2/spl times/4/spl times/8 mode by sharing the same data path with the 8/spl times/8 mode as much as possible. The proposed architecture also reduces the hardware and the chip size by exploiting the table look-up method instead of the extra multiplication circuits in the weighting coefficients handling. The implemented DCT/IDCT processor satisfies the accuracy specification of digital VCR.