While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another MOS transistor layer is fabricated on top of the bottom one, contamination risk and thermal stability issues appear, thus requiring adaptation of conductors/dielectrics for intermediate Back-End Of Line (iBEOL) processing. As materials differ from usual copper/low-k, it is necessary to study how standard cells electrical characteristics will be affected. We modeled different descriptions of iBEOL in 14nm FDSOI process and simulated standard cells characteristics. The average power consumption is almost the same while large cells with high drive timing degradation can be up to 20% in the worst case. This sensitivity analysis allowed us to identify which parameters (permittivity, resistivity) have the greatest impact depending on standard cell type and provide technology and design guidelines. Our goal here was to limit the performance degradation to around 5% maximum for the bottom tier standard cells.