Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits
| العنوان: | Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits |
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| المؤلفون: | Nobutaka Kito, Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi |
| المصدر: | IEEE Transactions on Applied Superconductivity. 33:1-5 |
| بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE), 2023. |
| سنة النشر: | 2023 |
| مصطلحات موضوعية: | Electrical and Electronic Engineering, Condensed Matter Physics, Electronic, Optical and Magnetic Materials |
| تدمد: | 2378-7074 1051-8223 |
| DOI: | 10.1109/tasc.2023.3245049 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::8c4beeb78a2146f520f3fba0a41163d6 https://doi.org/10.1109/tasc.2023.3245049 |
| Rights: | CLOSED |
| رقم الانضمام: | edsair.doi...........8c4beeb78a2146f520f3fba0a41163d6 |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 23787074 10518223 |
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| DOI: | 10.1109/tasc.2023.3245049 |