The expected large variations of electrical characteristics of sub-22 nm devices represents a limitation on future electronic circuits. This is particularly relevant on RAM memories that have to ensure both read stability and write ability of all the cells. In this paper we present a 6T-SRAM designed with 14nm FinFETs that makes use of the negative bit-line write assist technique allowing a reduction of the supply voltage without a degradation on neither speed nor stability. A new metric is introduced to quantify and control the drawbacks related to negative bit-line voltage. Additionally a new approach to predict the tails of the read current distribution under variability has been presented. Experimental results show that power consumption is reduced by 25% due to the decrease on the supply voltage.