High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015 [4], and reached 48 layers in 2016 [5]. Also, density as high as 2.62 and 4.29Gb/mm2 [5,6] were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: (1) four-block even-odd-combined row decoding to effectively address the increase of stacked layers; (2) unselected string pre-charge operation to improve endurance and reliability, and; (3) shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features.