In this paper, the design and implementation of low power and high-efficiency filterbank for MPEG-2/4 AAC system is presented. Since filterbank represents the most computation-intensive kernel of AAC codec, we design it with algorithm and architecture aspects. We supply the dedicated algorithm for filterbank. The derived algorithm and the hardware shared engine (HSE) we proposed for AAC can reduce the computation power and implement as a codec used in encoder and decoder. We also optimize the performance, hardware resources, and power consumption thoroughly. It is designed as an intellectual property (IP) to construct the overall decoder in an embedded system. The hardware cost is with 16.1 k logic gates, 2 k-word local memory, and 1 K-word coefficient ROM. The proposed design has a real-time operation at only 1.25 MHz with a sampling rate of 48 kHz. It can achieve 0.70 mW power consumption in TSMC 0.18 μm CMOS technology. Furthermore, we use a programmable chip (SOPC) platform which includes the software and hardware engine. Throughout the computation analysis, the bitstream parser and lower complexity part are performed by a software solution, and the higher complexity part is computed by a hardware solution. Several design techniques are needed including the wrapper design, embedded CPU, and IP to construct the system. Based on this co-design approach, a whole AAC audio decoder is also established.