A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.