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High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology

التفاصيل البيبلوغرافية
العنوان: High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology
المؤلفون: Kaya Can Akyel, M. Brocard, R. Boumchedda, G. Berhault, O. Billoint, Bastien Giraud, Sebastien Thuries, Edith Beigne, David Turgis, J.-P. Noel
المصدر: 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
بيانات النشر: IEEE, 2016.
سنة النشر: 2016
مصطلحات موضوعية: Engineering, Random access memory, Hardware_MEMORYSTRUCTURES, business.industry, 020208 electrical & electronic engineering, Spice, Transistor, High density, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 020202 computer hardware & architecture, law.invention, Robustness (computer science), law, Embedded system, Logic gate, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Static random-access memory, business
الوصف: In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and hold) of a 4T SRAM bitcell through post layout simulations. Results show that the proposed 3D 4T Bitcell offers 30% footprint reduction compared to the planar 6T SRAM bitcell in 14nm FD-SOI technology.
DOI: 10.1109/s3s.2016.7804376
URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::2118bf62b461a7ec7b1d48603301b37e
https://doi.org/10.1109/s3s.2016.7804376
رقم الانضمام: edsair.doi...........2118bf62b461a7ec7b1d48603301b37e
قاعدة البيانات: OpenAIRE
الوصف
DOI:10.1109/s3s.2016.7804376