In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning
| العنوان: | In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning |
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| المؤلفون: | Takahiro Hanyu, Sean C. Smithson, Warren J. Gross, Brett H. Meyer, Naoya Onizawa |
| المصدر: | IEEE Transactions on Circuits and Systems I: Regular Papers. 67:1541-1550 |
| بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE), 2020. |
| سنة النشر: | 2020 |
| مصطلحات موضوعية: | Digital electronics, Stochastic computing, Artificial neural network, business.industry, Computer science, 020208 electrical & electronic engineering, Activation function, 02 engineering and technology, Machine learning, computer.software_genre, Chip, Backpropagation, Reduction (complexity), CMOS, 0202 electrical engineering, electronic engineering, information engineering, Artificial intelligence, Electrical and Electronic Engineering, business, computer, Computer hardware |
| الوصف: | Deep Neural Networks (DNNs) have recently shown state-of-the-art results on various applications, such as computer vision and recognition tasks. DNN inference engines can be implemented in hardware with high energy efficiency as the computation can be realized using a low-precision fixed point or even binary precision with sufficient cognition accuracies. On the other hand, training DNNs using the well-known back-propagation algorithm requires high-precision floating-point computations on a CPU and/or GPU causing significant power dissipation (more than hundreds of kW) and long training time (several days or more). In this paper, we demonstrate a training chip fabricated using a commercial 65-nm CMOS technology for machine learning. The chip performs training without back propagation by using invertible logic with stochastic computing that can directly obtain weight values using input/output training data with low precision suitable for inference. When training neurons that compute the weighted sum of all inputs and then apply a non-linear activation function, our chip demonstrates a reduction of power dissipation and latency by 99.98% and 99.95%, respectively, in comparison with a state-of-the-art software implementation. |
| تدمد: | 1558-0806 1549-8328 |
| DOI: | 10.1109/tcsi.2019.2960383 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::19aef557355dfaab20888ee87a835b4f https://doi.org/10.1109/tcsi.2019.2960383 |
| Rights: | CLOSED |
| رقم الانضمام: | edsair.doi...........19aef557355dfaab20888ee87a835b4f |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 15580806 15498328 |
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| DOI: | 10.1109/tcsi.2019.2960383 |