التفاصيل البيبلوغرافية
| العنوان: |
Buried power rail integration for CMOS scaling beyond the 3 nm node |
| المؤلفون: |
Bannister, Julie, Mohanty, Nihar, Gupta, A., Tao, Z., Radisic, D., Mertens, H., Pedreira, O. Varela, Demuynck, S., Bömmels, J., Devriendt, K., Heylen, N., Wang, S., Kenis, K., Teugels, L., Sebaai, F., Lorant, C., Jourdan, N., Chan, B. T., Subramanian, S., Schleicher, F., Peter, A., Rassoul, N., Siew, Y., Briggs, B., Zhou, D., Rosseel, E., Capogreco, E., Mannaert, G., Sepúlveda, A., Dupuy, E., Vandersmissen, K., Chehab, B., Murdoch, G., Altamirano Sanchez, E., Biesemans, S., Tőkei, Zs., Litta, E. Dentoni, Horiguchi, N. |
| المصدر: |
Proceedings of SPIE; May 2022, Vol. 12056 Issue: 1 p120560B-120560B-5, 1085046p |
| قاعدة البيانات: |
Supplemental Index |