Academic Journal
A New Approach to Parallel Processing
| العنوان: | A New Approach to Parallel Processing |
|---|---|
| المؤلفون: | William C. Cave, Robert E. Wassmer, Henry F. Ledgard, Alan B. Salisbury, Kenneth T. Irvine, Michael A. Mulshine |
| المصدر: | IEEE Access, Vol 8, Pp 30287-30305 (2020) |
| بيانات النشر: | IEEE, 2020. |
| سنة النشر: | 2020 |
| المجموعة: | LCC:Electrical engineering. Electronics. Nuclear engineering |
| مصطلحات موضوعية: | Application space architecture, data structures, engineering drawings, instruction set architecture, module independence, parallel processing, Electrical engineering. Electronics. Nuclear engineering, TK1-9971 |
| الوصف: | The Application Space Architecture (ASA) defines parallel processor design as an adjunct to the Instruction Set Architectures (ISA) defined by Von Neumann for single processors. Before addressing hardware, one must understand applications requiring parallel processors, and software approaches required to meet speed constraints. Parallel processor applications use a single task to run N (number-of-processors) times faster than could be done on a single processor, where Processor Utilization Efficiency (PUE) is the ratio of single processor time to parallel processor time divided by N. Such applications require processing to be split into independent elements running in parallel on a large number of processors. This requires that processors do not sit idle (current PUEs are typically 2-10%.) This sets the requirement for “independent” elements to communicate with each other without stopping. In special cases, clusters of PCs are used to perform parametric analyses running many copies of a simulation on separate computers, typically using different random numbers. Except for initial and terminal processes, these separate simulations hardly communicate while running. Thus they are easily divided into separate tasks that typically exchange information between computers passing data or messages through a top level management task. Such applications (e.g., LINPACK) are labeled “embarrassingly parallel”. |
| نوع الوثيقة: | article |
| وصف الملف: | electronic resource |
| اللغة: | English |
| تدمد: | 2169-3536 |
| Relation: | https://ieeexplore.ieee.org/document/8985544/; https://doaj.org/toc/2169-3536 |
| DOI: | 10.1109/ACCESS.2020.2972204 |
| URL الوصول: | https://doaj.org/article/782544d8e409488591b39dff1b14cb97 |
| رقم الانضمام: | edsdoj.782544d8e409488591b39dff1b14cb97 |
| قاعدة البيانات: | Directory of Open Access Journals |
Full Text Finder | ResultId |
1 |
|---|---|
| Header |
edsdoj Directory of Open Access Journals edsdoj.782544d8e409488591b39dff1b14cb97 930 3 Academic Journal academicJournal 930.017944335938 |
| PLink |
https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsdoj&AN=edsdoj.782544d8e409488591b39dff1b14cb97&custid=s6537998&authtype=sso |
| FullText |
Array
(
[Availability] => 0
)
Array ( [0] => Array ( [Url] => https://doaj.org/article/782544d8e409488591b39dff1b14cb97 [Name] => EDS - DOAJ [Category] => fullText [Text] => View record in DOAJ [MouseOverText] => View record in DOAJ ) [1] => Array ( [Url] => https://resolver.ebscohost.com/openurl?custid=s6537998&groupid=main&authtype=ip,guest&sid=EBSCO:edsdoj&genre=article&issn=21693536&ISBN=&volume=8&issue=&date=20200101&spage=30287&pages=30287-30305&title=IEEE Access&atitle=A%20New%20Approach%20to%20Parallel%20Processing&id=DOI:10.1109/ACCESS.2020.2972204 [Name] => Full Text Finder (s6537998api) [Category] => fullText [Text] => Full Text Finder [Icon] => https://imageserver.ebscohost.com/branding/images/FTF.gif [MouseOverText] => Full Text Finder ) ) |
| Items |
Array
(
[Name] => Title
[Label] => Title
[Group] => Ti
[Data] => A New Approach to Parallel Processing
)
Array ( [Name] => Author [Label] => Authors [Group] => Au [Data] => <searchLink fieldCode="AR" term="%22William+C%2E+Cave%22">William C. Cave</searchLink><br /><searchLink fieldCode="AR" term="%22Robert+E%2E+Wassmer%22">Robert E. Wassmer</searchLink><br /><searchLink fieldCode="AR" term="%22Henry+F%2E+Ledgard%22">Henry F. Ledgard</searchLink><br /><searchLink fieldCode="AR" term="%22Alan+B%2E+Salisbury%22">Alan B. Salisbury</searchLink><br /><searchLink fieldCode="AR" term="%22Kenneth+T%2E+Irvine%22">Kenneth T. Irvine</searchLink><br /><searchLink fieldCode="AR" term="%22Michael+A%2E+Mulshine%22">Michael A. Mulshine</searchLink> ) Array ( [Name] => TitleSource [Label] => Source [Group] => Src [Data] => IEEE Access, Vol 8, Pp 30287-30305 (2020) ) Array ( [Name] => Publisher [Label] => Publisher Information [Group] => PubInfo [Data] => IEEE, 2020. ) Array ( [Name] => DatePubCY [Label] => Publication Year [Group] => Date [Data] => 2020 ) Array ( [Name] => Subset [Label] => Collection [Group] => HoldingsInfo [Data] => LCC:Electrical engineering. Electronics. Nuclear engineering ) Array ( [Name] => Subject [Label] => Subject Terms [Group] => Su [Data] => <searchLink fieldCode="DE" term="%22Application+space+architecture%22">Application space architecture</searchLink><br /><searchLink fieldCode="DE" term="%22data+structures%22">data structures</searchLink><br /><searchLink fieldCode="DE" term="%22engineering+drawings%22">engineering drawings</searchLink><br /><searchLink fieldCode="DE" term="%22instruction+set+architecture%22">instruction set architecture</searchLink><br /><searchLink fieldCode="DE" term="%22module+independence%22">module independence</searchLink><br /><searchLink fieldCode="DE" term="%22parallel+processing%22">parallel processing</searchLink><br /><searchLink fieldCode="DE" term="%22Electrical+engineering%2E+Electronics%2E+Nuclear+engineering%22">Electrical engineering. Electronics. Nuclear engineering</searchLink><br /><searchLink fieldCode="DE" term="%22TK1-9971%22">TK1-9971</searchLink> ) Array ( [Name] => Abstract [Label] => Description [Group] => Ab [Data] => The Application Space Architecture (ASA) defines parallel processor design as an adjunct to the Instruction Set Architectures (ISA) defined by Von Neumann for single processors. Before addressing hardware, one must understand applications requiring parallel processors, and software approaches required to meet speed constraints. Parallel processor applications use a single task to run N (number-of-processors) times faster than could be done on a single processor, where Processor Utilization Efficiency (PUE) is the ratio of single processor time to parallel processor time divided by N. Such applications require processing to be split into independent elements running in parallel on a large number of processors. This requires that processors do not sit idle (current PUEs are typically 2-10%.) This sets the requirement for “independent” elements to communicate with each other without stopping. In special cases, clusters of PCs are used to perform parametric analyses running many copies of a simulation on separate computers, typically using different random numbers. Except for initial and terminal processes, these separate simulations hardly communicate while running. Thus they are easily divided into separate tasks that typically exchange information between computers passing data or messages through a top level management task. Such applications (e.g., LINPACK) are labeled “embarrassingly parallel”. ) Array ( [Name] => TypeDocument [Label] => Document Type [Group] => TypDoc [Data] => article ) Array ( [Name] => Format [Label] => File Description [Group] => SrcInfo [Data] => electronic resource ) Array ( [Name] => Language [Label] => Language [Group] => Lang [Data] => English ) Array ( [Name] => ISSN [Label] => ISSN [Group] => ISSN [Data] => 2169-3536 ) Array ( [Name] => NoteTitleSource [Label] => Relation [Group] => SrcInfo [Data] => https://ieeexplore.ieee.org/document/8985544/; https://doaj.org/toc/2169-3536 ) Array ( [Name] => DOI [Label] => DOI [Group] => ID [Data] => 10.1109/ACCESS.2020.2972204 ) Array ( [Name] => URL [Label] => Access URL [Group] => URL [Data] => <link linkTarget="URL" linkTerm="https://doaj.org/article/782544d8e409488591b39dff1b14cb97" linkWindow="_blank">https://doaj.org/article/782544d8e409488591b39dff1b14cb97</link> ) Array ( [Name] => AN [Label] => Accession Number [Group] => ID [Data] => edsdoj.782544d8e409488591b39dff1b14cb97 ) |
| RecordInfo |
Array
(
[BibEntity] => Array
(
[Identifiers] => Array
(
[0] => Array
(
[Type] => doi
[Value] => 10.1109/ACCESS.2020.2972204
)
)
[Languages] => Array
(
[0] => Array
(
[Text] => English
)
)
[PhysicalDescription] => Array
(
[Pagination] => Array
(
[PageCount] => 19
[StartPage] => 30287
)
)
[Subjects] => Array
(
[0] => Array
(
[SubjectFull] => Application space architecture
[Type] => general
)
[1] => Array
(
[SubjectFull] => data structures
[Type] => general
)
[2] => Array
(
[SubjectFull] => engineering drawings
[Type] => general
)
[3] => Array
(
[SubjectFull] => instruction set architecture
[Type] => general
)
[4] => Array
(
[SubjectFull] => module independence
[Type] => general
)
[5] => Array
(
[SubjectFull] => parallel processing
[Type] => general
)
[6] => Array
(
[SubjectFull] => Electrical engineering. Electronics. Nuclear engineering
[Type] => general
)
[7] => Array
(
[SubjectFull] => TK1-9971
[Type] => general
)
)
[Titles] => Array
(
[0] => Array
(
[TitleFull] => A New Approach to Parallel Processing
[Type] => main
)
)
)
[BibRelationships] => Array
(
[HasContributorRelationships] => Array
(
[0] => Array
(
[PersonEntity] => Array
(
[Name] => Array
(
[NameFull] => William C. Cave
)
)
)
[1] => Array
(
[PersonEntity] => Array
(
[Name] => Array
(
[NameFull] => Robert E. Wassmer
)
)
)
[2] => Array
(
[PersonEntity] => Array
(
[Name] => Array
(
[NameFull] => Henry F. Ledgard
)
)
)
[3] => Array
(
[PersonEntity] => Array
(
[Name] => Array
(
[NameFull] => Alan B. Salisbury
)
)
)
[4] => Array
(
[PersonEntity] => Array
(
[Name] => Array
(
[NameFull] => Kenneth T. Irvine
)
)
)
[5] => Array
(
[PersonEntity] => Array
(
[Name] => Array
(
[NameFull] => Michael A. Mulshine
)
)
)
)
[IsPartOfRelationships] => Array
(
[0] => Array
(
[BibEntity] => Array
(
[Dates] => Array
(
[0] => Array
(
[D] => 01
[M] => 01
[Type] => published
[Y] => 2020
)
)
[Identifiers] => Array
(
[0] => Array
(
[Type] => issn-print
[Value] => 21693536
)
)
[Numbering] => Array
(
[0] => Array
(
[Type] => volume
[Value] => 8
)
)
[Titles] => Array
(
[0] => Array
(
[TitleFull] => IEEE Access
[Type] => main
)
)
)
)
)
)
)
|
| IllustrationInfo |