Academic Journal
Computationally Efficient Low-Power Sigma-Delta Modulation-Based Image Noise Removal Filter.
| العنوان: | Computationally Efficient Low-Power Sigma-Delta Modulation-Based Image Noise Removal Filter. |
|---|---|
| المؤلفون: | Pathan, Aneela, Memon, Tayab D., Shah, Syed Haseeb, Mangi, Rizwan Aziz |
| المصدر: | Circuits, Systems & Signal Processing; Feb2025, Vol. 44 Issue 2, p1103-1119, 17p |
| مصطلحات موضوعية: | DELTA-sigma modulation, IMAGE reconstruction, NETWORKS on a chip, NOISE control, IMAGE processing |
| مستخلص: | Image degradation, caused by various factors, often results in noise and blur. For image restoration, inverse filters are typically used, while Wiener filters are employed for noise reduction. Unlike text or voice processing, image processing deals with significantly larger data volumes, necessitating greater computational resources. This demand can saturate resource-limited hardware such as FPGAs and ASICs, making architectural optimization essential for designing a complete System on Chip or Network on Chip. Although several hardware optimization methods exist in the literature, each has its limitations. Sigma-Delta Modulation has emerged as a promising technique in recent years, particularly for reducing the complexity of DSP systems by shortening word lengths from multi-bit to single-bit. This reduction simplifies systems and conserves hardware resources. While SDM has been widely applied in various domains, including basic arithmetic and complex adaptive filters, its use has been largely confined to speech and text processing. In recent work, the authors proposed a novel application of SDM in image processing. This study extends that investigation by designing a single-bit SDM-based Wiener filter for image noise reduction. The proposed single-bit filter is functionally compared against traditional Wiener filters, Steepest-Descent filters, and Adaptive Mean filters. Key statistical metrics such as noise variance, signal-to-noise ratio, Mean Squared Error, and Peak SNR are simulated and analyzed for real-time performance evaluation. The results demonstrate that the proposed single-bit technique remains robust against noise in dynamic environments. An FPGA-based implementation of the single-bit system further highlights its efficiency, requiring fewer resources and consuming less operational power. The findings confirm that the proposed design outperforms conventional methods in terms of effectiveness, statistical performance, and resource-optimized implementation, thereby enhancing its acceptability and robustness. The study is further strengthened by qualitative and quantitative analyses, with simulation results clearly illustrating the advantages of the proposed single-bit filter over conventional multi-bit approaches. [ABSTRACT FROM AUTHOR] |
| Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| قاعدة البيانات: | Complementary Index |
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