المؤلفون: Michael A. Kochte, Miyase, Kohei, Wen, Xiaoqing, Kajihara, Seiji, Yamato, Yuta, Enokimoto, Kazunari, Wunderlich, Hans-Joachim

مصطلحات موضوعية: VLSI, integrated circuit testing, low-power electronics, SAT-based capture-power reduction, VLSI testing, X-identification, at-speed broadcast-scan-based test compression architectures, low power devices, power dissipation, power management, power-aware X-filling, power-aware testing, test cubes, test vectors, Automatic test pattern generation, Circuit faults, Flip-flops, Integrated circuit modeling, Logic gates, Switches, ATPG, Low capture-power test, X-filling

وصف الملف: application/pdf

Relation: http://hdl.handle.net/10061/11178; 33; 38

الاتاحة: http://hdl.handle.net/10061/11178

المؤلفون: Michael, A. Kochte, Miyase, Kohei, Wen, Xiaoqing, Kajihara, Seiji, Yamato, Yuta, Enokimoto, Kazunari, Wunderlich, Hans-Joachim

مصطلحات الفهرس: VLSI, integrated circuit testing, low-power electronics, SAT-based capture-power reduction, VLSI testing, X-identification, at-speed broadcast-scan-based test compression architectures, low power devices, power dissipation, power management, power-aware X-filling, power-aware testing, test cubes, test vectors, Automatic test pattern generation, Circuit faults, Flip-flops, Integrated circuit modeling, Logic gates, Switches, ATPG, Low capture-power test, X-filling, Conference Paper, AM

URL: http://hdl.handle.net/10061/11178
https://naist.repo.nii.ac.jp/?action=repository_action_common_download&item_id=4909&item_no=1&attribute_id=17&file_no=1
https://doi.org/10.1109/ISLPED.2011.5993600
https://doi.org/10.1109/ISLPED.2011.5993600

المؤلفون: Kochte, Michael A., Miyase, Kohei, Wen, Xiaoqing, Kajihara, Seiji, 20707244, Yamato, Yuta, Enokimoto, Kazunari, Wunderlich, Hans-Joachim

مصطلحات الفهرس: VLSI, integrated circuit testing, low-power electronics, SAT-based capture-power reduction, VLSI testing, X-identification, at-speed broadcast-scan-based test compression architectures, low power devices, power dissipation, power management, power-aware X-filling, power-aware testing, test cubes, test vectors, Automatic test pattern generation, Circuit faults, Flip-flops, Integrated circuit modeling, Logic gates, Switches, ATPG, Low capture-power test, X-filling, Conference Paper, AM

URL: http://hdl.handle.net/10061/11178
https://naist.repo.nii.ac.jp/records/4909
https://naist.repo.nii.ac.jp/record/4909/files/fp180-kochte.pdf
https://doi.org/10.1109/ISLPED.2011.5993600
https://doi.org/10.1109/ISLPED.2011.5993600