المؤلفون: Lingshan Kong, Yong Chen, Haohong Yu, Chirn Chye Boon, Pui-In Mak, Rui P. Martins

المصدر: IEEE Access, Vol 9, Pp 35814-35823 (2021)

مصطلحات موضوعية: CMOS, high-speed transceiver, variable-gain amplifier (VGA), negative capacitance (NC), peak-to-peak jitter, data-dependent jitter (DDJ), Electrical engineering. Electronics. Nuclear engineering, TK1-9971

وصف الملف: electronic resource

Relation: https://ieeexplore.ieee.org/document/9363870/; https://doaj.org/toc/2169-3536

URL الوصول: https://doaj.org/article/ec0f698f4da84b11ac79ca1b5ede0274

المؤلفون: Sui, Chunchun, Ren, Liehui, Gao, Xu, Pan, Jingnan, Drewniak, James L., Beetner, Daryl G.

المصدر: Electrical and Computer Engineering Faculty Research & Creative Works

مصطلحات موضوعية: Bit error rate, Computation theory, Computer circuits, Errors, Forecasting, Logic circuits, Optical communication, Printed circuit boards, Printed circuits, Reconfigurable hardware, Statistics, Computational effort, High-speed devices, Mean and standard deviations, Mean standard deviation, Peak-to-peak jitter, Printed circuit boards (PCB), Simultaneous switching noise, Statistical characteristics, Jitter, Analytical models, field programmable logic array, integrated circuit (IC) noise, noise measurement, power distribution, statistical analysis, Electrical and Computer Engineering

Relation: https://scholarsmine.mst.edu/ele_comeng_facwork/2178; https://doi.org/10.1109/TEMC.2015.2474124

الاتاحة: https://scholarsmine.mst.edu/ele_comeng_facwork/2178
https://doi.org/10.1109/TEMC.2015.2474124

المؤلفون: Chen I.-F., Yang R.-J., Liu S.-I.

المساهمون: 國立臺灣科技大學電機工程系

مصطلحات موضوعية: 1.25 Gb/s, Bit rates, Chip areas, Clock and data recovery circuit, CMOS technology, Digital clocks, Jitter performance, Latency reduction, Loop filter, Loop stability, Low speed, Peak-to-peak jitter, Phase margins, Unit intervals, CMOS integrated circuits, Jitter, Signal receivers, Digital circuits

Relation: 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009,pp.309-312, Taipei; http://ir.lib.ntust.edu.tw/handle/987654321/26768; http://ir.lib.ntust.edu.tw/bitstream/987654321/26768/-1/index.html

الاتاحة: http://ir.lib.ntust.edu.tw/handle/987654321/26768
http://ir.lib.ntust.edu.tw/bitstream/987654321/26768/-1/index.html

المؤلفون: 陳煥達, Huan-Ta Chen

المساهمون: 吳仁銘, Jen-Ming Wu

مصطلحات موضوعية: 鎖相迴路, 雙模, 平衡直流電壓, 抖動, 峰對峰值抖動, 射頻式互補式金氧半電晶體, 接地式共平面波導, PLL, dual mode, dc-balance, jitter, peak to peak jitter, RFCMOS, GCPW

Time: 46

وصف الملف: 155 bytes; text/html

Relation: [1] C. S. Chang, D. S. Lee and Y. S. Jou, “Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering,” Computer Communications, Vol. 25, pp. 611-622, 2002 [2] C. S. Chang, D. S. Lee and C. M. Lien, “Load balanced Birkhoff-von Neumann switch, part II: Multi-stage buffering,” Computer Communications, Vol. 25, pp. 623-634, 2002. [3] C. S. Chang, D. S. Lee and Y. J. Shih, “Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets,” Infocom, 2003. [4] Yu-Chen Chiang, “Jitter Performance Study For Phase-Lock Loop,” NTHU Master Thesis, 2004. [5] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 1st edition, 2004. [6] Alvin L. S. Loke, Robert K. Barnes,Tin Tin Wee, Michael M. Oshima, Charles E. Moore,Ronald R. Kennedy, and Michael J. Gilsdorf, “A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUG. 2006. [7] Shen-Sz Wang, “Voltage Controlled Oscillator (VCO) Design and the Impact of Substrate Noise Coupling on VCO,” NTHU Master Thesis, 2005. [8] Francesco Svelto, Stefano Deantoni, Rinaldo Castello, “A 1.3 GHz Low-Phase Noise Fully Tunable CMOS LC VCO,” IEEE JOURNAL ON SOLID STATE CIRCUITS, VOL. 35, NO. 3, MAR. 2000. [9] Remco C. H. van de Beek, Cicero S. Vaucher, Domine M. W. Leenaerts, Eric A. M. Klumperink, and Bram Nauta, “A 2.5–10-GHz Clock Multiplier Unit With 0.22-psRMS Jitter in Standard 0.18-_m CMOS” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOV. 2004. [10] Ahmed Helmy and Mohammed Ismail, ” A Design Guide for Reducing Substrate Noise Coupling in RF Applications,” IEEE CIRCUITS & DEVICES MAGAZINE, pp. 7-21, SEP./OCT. 2006 [11] Hung-Wen Lu, Chau-Chin Su, “A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type Multiplexer”, 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 2004 [12] A.L. Coban, M.H. Koroglu, K.A. Ahmed, “A 2.5-3.125Gb/s Quad Transceiver with Second Order Analog DLL Based CDRs”, Custom Integrated Circuits Conference, 2004. [13] Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, C.S.G. Conroy, Beomsup Kim, “A Four-Channel 3.125Gb/s/ch CMOS Serial-Link Transceiver With a Mixed-Mode Adaptive Equalizer”, Solid-State Circuits, IEEE Journal of Volume 40, Issue 2, Feb. 2005 [14] A.L. Coban, M.H. Koroglu, K.A. Ahmed, “A 2.5-3.125Gb/s Quad Transceiver with Second Order Analog DLL Based CDRs”, IEEE Journal of Solid-State Circuits, Volume 40, Issue 9, Sept. 2005. [15] Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, C.S.G. Conroy, Beomsup Kim, “A Four-Channel 3.125Gb/s/ch CMOS Serial-Link Transceiver With a Mixed-Mode Adaptive Equalizer”, IEEE Journal of Solid-State Circuits, Volume 40, Issue 2, Feb. 2005 [16] Yohan Frans, Nhat Nguyen, Barry Daly, Yueyong Wang, Dennis Kim, Todd Bystrom, Dennis Olarte, Kevin Donnelly, "A 1-4 Gbps Quad Transceiver Cell using PLL with Gate Current Leakage Compensator in 90nm CMOS", Symposium On VLSI Circuits Digest of Technical Papers, pp. 134-137, June. 2004 [17] Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos, "A 0.4–4-Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs", IEEE Journal of Solid-State Circuits, Volume 38, Issue 5, pp. 747-754, May 2003; http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/30167

الاتاحة: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/30167