المؤلفون: Sandberg, Andreas, 1984, Hagersten, Erik, Black-Schaffer, David

المصدر: UPMARC CoDeR-MP Technical report / Department of Information Technology, Uppsala University.

مصطلحات موضوعية: Computer Architecture, Simulation, Sampling, Native Execution, Virtualization, pFSA, FSA, KVM, Computer Systems, Datorteknik

وصف الملف: electronic

URL الوصول: https://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-220649
http://www.it.uu.se/research/publications/reports/2014-005/2014-005-nc.pdf
https://uu.diva-portal.org/smash/get/diva2:705982/FULLTEXT01.pdf

المؤلفون: Gavriilidis, Haralampos

مصطلحات موضوعية: dataflow engines, data exchange, computation offloading, native execution

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::07ba01035de36a9265b6915f60e68487

المؤلفون: Bacivarov, I., Yoo, S., Jerraya, A.A.

المساهمون: Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)

المصدر: Proceedings-Seventh-IEEE-International-High-Level-Design-Validation-and-Test-Workshop ; https://hal.science/hal-00008057 ; 2002, pp.51-6

مصطلحات موضوعية: timed-hardware-software-cosimulation, instruction-set-simulator, native-execution, SoC-design, operating-systems, timing-simulation, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

الاتاحة: https://hal.science/hal-00008057

المؤلفون: Gerin, P.

المساهمون: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Institut National Polytechnique de Grenoble - INPG, F. Pétrot(Frederic.Petrot@imag.fr), Torella, Lucie, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)

المصدر: Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble-INPG, 2009. Français

مصطلحات موضوعية: annotation, Exécution native, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, modélisation TLM, instrumentation automatique de logiciel, automatic software instrumentation, MPSOC simulation, SoC, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, TLM models, native execution

وصف الملف: application/pdf

URL الوصول: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::1c2bfe7cacb63de89448550bb9d47c3e
https://tel.archives-ouvertes.fr/tel-00558777

المؤلفون: Bacivarov, I., Bouchhima, A., Yoo, S., Jerraya, A.A.

المساهمون: Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)

المصدر: ISSN: 1741-1068.

مصطلحات موضوعية: SoC validation, SOC verification, hardware-software cosimulation, HAL simulation model, timed native execution, timing accuracy, system-on-chip, embedded systems, SOC design, PACS 85.42, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

الاتاحة: https://hal.science/hal-00105154

المؤلفون: Gerin, P.

المساهمون: Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS), Institut National Polytechnique de Grenoble - INPG, F. Pétrot(Frederic.Petrot@imag.fr)

المصدر: https://theses.hal.science/tel-00558777 ; Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2009. Français. ⟨NNT : ⟩.

مصطلحات موضوعية: native execution, TLM models, automatic software instrumentation, SoC, MPSOC simulation, Exécution native, modélisation TLM, instrumentation automatique de logiciel, annotation, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

الاتاحة: https://theses.hal.science/tel-00558777
https://theses.hal.science/tel-00558777v1/document
https://theses.hal.science/tel-00558777v1/file/sms_0316.pdf

المؤلفون: Veenstra, Jack E., Fowler, Robert J.

مصطلحات موضوعية: event-driven memory hierarchy simulators, front end, memory reference events, native execution, processor simulation, shared-memory multiprocessors, software interpretation, software package, standard Unix, executable files, uniprocessor hosts, user-provided memory system simulator, discrete event simulation, performance evaluation, virtual machines, MINT, MIPS R3000 based multiprocessor, efficient simulation, shared memory systems

Relation: http://hdl.handle.net/1802/1455; Veenstra, Jack E., Fowler, Robert J., MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors, Proc., 2nd Int'l. Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), Durham, NC, January 1994, 201--207.

الاتاحة: http://hdl.handle.net/1802/1455

المؤلفون: Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya, Iuliana Bacivarov

المساهمون: Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Torella, Lucie

المصدر: International Journal of Embedded Systems
International Journal of Embedded Systems, Inderscience, 2005, Volume: 1-Issue: 1/2, pp.103-111

مصطلحات موضوعية: hardware-software cosimulation, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 02 engineering and technology, 01 natural sciences, Instruction set, system-on-chip, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, System on a chip, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, business.industry, SOC design, timing accuracy, 020202 computer hardware & architecture, HAL simulation model, Computer architecture, SOC verification, timed native execution, Hardware and Architecture, PACS 85.42, Embedded system, Key (cryptography), embedded systems, Design cycle, business, SoC validation, Software

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c5c767e2b6f798d8ac7ee8123c2c9d92
https://doi.org/10.1504/ijes.2005.008812

المؤلفون: Veenstra, Jack E., Fowler, Robert J.

مصطلحات الفهرس: event-driven memory hierarchy simulators, front end, memory reference events, native execution, processor simulation, shared-memory multiprocessors, software interpretation, software package, standard Unix, executable files, uniprocessor hosts, user-provided memory system simulator, discrete event simulation, performance evaluation, virtual machines, MINT, MIPS R3000 based multiprocessor, efficient simulation, shared memory systems, Technical Report

URL: http://hdl.handle.net/1802/1455

المؤلفون: Veenstra, Jack E., Fowler, Robert J.

مصطلحات الفهرس: event-driven memory hierarchy simulators, front end, memory reference events, native execution, processor simulation, shared-memory multiprocessors, software interpretation, software package, standard Unix, executable files, uniprocessor hosts, user-provided memory system simulator, discrete event simulation, performance evaluation, virtual machines, MINT, MIPS R3000 based multiprocessor, efficient simulation, shared memory systems, Technical Report

URL: http://hdl.handle.net/1802/1455