يعرض 1 - 16 نتائج من 16 نتيجة بحث عن '"multiple transitions"', وقت الاستعلام: 0.48s تنقيح النتائج
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    Academic Journal
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    Academic Journal
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    Academic Journal

    المصدر: Proceedings of the National Academy of Sciences of the United States of America, 2008 Nov 01. 105(45), 17245-17249.

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    Academic Journal
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    Book

    المصدر: Jindal-Snape , D , Johnston , B , Pringle , J , Gold , L , Grant , J , Scott , R , Carragher , P & Dempsey , R 2015 , Multiple and Multi-dimensional transitions : Understanding the life transitions of young adults cared for by CHAS and the impact on their parents, siblings and professionals . University of Dundee , Dundee .

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    Academic Journal

    المساهمون: Roberts, R

    المصدر: J. Chem. Phys. 53: 1937-40(1 Sep 1970).; Other Information: Orig. Receipt Date: 31-DEC-70

    وصف الملف: Medium: X

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    Dissertation/ Thesis

    المؤلفون: 李晨豪, Lee, Chen-Hao

    المساهمون: 黃鐘揚, 臺灣大學:電子工程學研究所

    وصف الملف: 1001444 bytes; application/pdf

    Relation: Reference [1] J. Cong, L. He, K. Y. Khoo, C. K. Koh and Z. Pan, “Interconnect Design for Deep Submicron ICs”, Proc. IEEE Int'l Conf. on Computer-Aided Design, San Jose, California, pp. 478-485, November 1997. [2] 陳麒旭, “靜態時序分析(Static Timing Analysis)基礎及應用”, http://www.chip123.com/article/Static Timing Analysis01.htm [3] MiniSAT page, http://www.cs.chalmers.se/Cs/Research/FormalMethods/MiniSat/ [4] Eun Sei Park, M. Ray Mercer, "An Efficient Delay Test Generation System for Combinational Logic Circuits", Annual ACM IEEE Design Automation Conference [5] Perl 入門與實作, http://linux.tnc.edu.tw/techdoc/perl_intro/ [6] HSPICE simulation, http://www.ee.vt.edu/~ha/cadtools/hspice/hspice.html [7] MATALB programming, http://www.cs.nthu.edu.tw/~jang/mlbook/ [8] Dongwoo Lee, Vladimir Zolotov, David Blaauw, "Static Timing Analysis using Backward Signal Propagation", University of Michigan, Ann Arbor, MI *Motorola Inc. Austin, TX [9] W. B. Jone, W. S. Yeh, C. W. Yeh*, and S. R. Das**, "An Adaptive Path Select ion Met hod for Delay Testing",Dept. of CS&IE, National Chung-Cheng U., Taiwan, R.O.C.*, Dept. of EE, U. of Ottawa, Ottawa, Ontario, K1N 6N5, Canada** [10] Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira, Karem A. Sakallah, "Satisfiability models and algorithms for circuit delay computation", ACM Transactions on Design Automation of Electronic Systems (TODAES) 2002. [11] Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato, “Path delay test compaction with process variation tolerance”, Annual ACM IEEE Design Automation Conference, 2005. [12] 黃俊輔, “Quick RTL Synthesis for Design Analysis and Verification”, 國立台灣大學電機工程學研究所碩士論文.; en-US; http://ntur.lib.ntu.edu.tw/handle/246246/57610; http://ntur.lib.ntu.edu.tw/bitstream/246246/57610/1/ntu-96-R93943162-1.pdf

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    Electronic Resource
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