المؤلفون: Miettinen, Pekka

المساهمون: Honkala, Mikko, DSc., Aalto University, Department of Radio Science and Engineering, Finland, Roos, Janne, Dr., Aalto University, Department of Radio Science and Engineering, Finland, Sähkötekniikan korkeakoulu, School of Electrical Engineering, Radiotieteen ja -tekniikan laitos, Department of Radio Science and Engineering, Valtonen, Martti, Prof., Aalto University, Department of Radio Science and Engineering, Finland, Circuit Theory, Piiriteoria, Aalto-yliopisto, Aalto University

مصطلحات موضوعية: Electrical engineering, circuit simulation, interconnect modeling, model-order reduction, piirisimulointi, liitinjohtomallinnus, malliredusointi

وصف الملف: application/pdf

Relation: Aalto University publication series DOCTORAL DISSERTATIONS; 10/2014; [Publication 1]: P. Miettinen, M. Honkala, J. Roos, C. Neff, and A. Basermann. Study and development of an efficient RC-in–RC-out MOR method. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS’08, Malta, pp. 1277–1280, Aug. 2008.; [Publication 2]: P. Miettinen, M. Honkala, and J. Roos. Partitioning-based RL-in–RL-out MOR method. Mathematics in Industry 14: Scientific Computing in Electrical Engineering SCEE 2008, J. Roos and L. R. J. Costa, Eds. Berlin, Germany: Springer-Verlag, pp. 547–554, Jan. 2010.; [Publication 3]: M. Honkala, P. Miettinen, J. Roos, and C. Neff. Hierarchical model-order reduction flow. Mathematics in Industry 14: Scientific Computing in Electrical Engineering SCEE 2008, J. Roos and L. R. J. Costa, Eds. Berlin, Germany: Springer-Verlag, pp. 539–546, Jan. 2010.; [Publication 4]: P. Miettinen, M. Honkala, J. Roos, and M. Valtonen. PartMOR: Partitioning-based realizable model-order reduction method for RLC circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 3, pp. 374–387, March 2011.; [Publication 5]: P. Miettinen, M. Honkala, J. Roos, and M. Valtonen. Improving model-order reduction methods by singularity exclusion. Mathematics in Industry 16: Scientific Computing in Electrical Engineering SCEE 2010, B. Michielsen and J. -R. Poirier, Eds. Berlin, Germany: Springer-Verlag, pp. 395–404, Jan. 2012.; [Publication 6]: P. Miettinen, M. Honkala, J. Roos, and M. Valtonen. Partitioning-based reduction of circuits with mutual inductances. Mathematics in Industry 16: Scientific Computing in Electrical Engineering SCEE 2010, B. Michielsen and J. -R. Poirier, Eds. Berlin, Germany: Springer-Verlag, pp. 395–404, Jan. 2012.; [Publication 7]: P. Miettinen, M. Honkala, J. Roos, and M. Valtonen. Sparsification of dense capacitive coupling of interconnects. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 10, pp. 1955–1959, Oct. 2013.; [Publication 8]: P. Miettinen, M. Honkala, J. Roos, and M. Valtonen. Realizable reduction of interconnect models with dense coupling. In European Conference on Circuit Theory and Design (ECCTD) 2013, Dresden, Germany, pp. 1–4, Sept. 2013.; 1799-4942 (electronic); 1799-4934 (printed); 1799-4934 (ISSN-L); https://aaltodoc.aalto.fi/handle/123456789/12442; URN:ISBN:978-952-60-5541-1

الاتاحة: https://aaltodoc.aalto.fi/handle/123456789/12442

المؤلفون: Hällström, Lassi

المساهمون: Miettinen, Pekka, Sähkötekniikan korkeakoulu, Turunen, Markus, Aalto-yliopisto, Aalto University

مصطلحات موضوعية: elektroninen piiri, malliredusointi, simulointi, siirtolinja

وصف الملف: application/pdf

Relation: https://aaltodoc.aalto.fi/handle/123456789/13291; URN:NBN:fi:aalto-201406032045

الاتاحة: https://aaltodoc.aalto.fi/handle/123456789/13291

المؤلفون: Honkala, Mikko

المساهمون: Roos, Janne, D.Sc. (Tech.), Aalto University, Finland, Sähkötekniikan korkeakoulu, School of Electrical Engineering, Radiotieteen ja -tekniikan laitos, Department of Radio Science and Engineering, Valtonen, Martti, Prof., Aalto University, Finland, Aalto-yliopisto, Aalto University

مصطلحات موضوعية: Electrical engineering, circuit simulation, numerical analysis, parallel processing, iterative methods, model-order reduction, preconditioners, Piirisimulointi, numeerinen analyysi, rinnakkaislaskenta, iteratiiviset menetelmät, malliredusointi, pohjustimetnaeos, nulla

وصف الملف: 75 + app. 82; application/pdf

Relation: Aalto University publication series DOCTORAL DISSERTATIONS; 174/2012; [Publication 1]: M. Honkala. Nonmonotone norm-reduction method for circuit simulation. Electronics Letters, vol. 38, pp. 1316–1317, Oct. 2002.; [Publication 2]: M. Honkala, J. Roos, and V. Karanko. On nonlinear iteration methods for DC analysis of industrial circuits. Mathematics in Industry 8: Progress in Industrial Mathematics at ECMI 2004, (A. D. Bucchianico, R. M. M. Mattheij, and M. A. Peletier, eds.), pp. 144–148, 2006.; [Publication 3]: M. Honkala, J. Roos, and M. Valtonen. New multilevel Newton–Raphson method for parallel circuit simulation. Proceedings of European Conference on Circuit Theory and Design, vol. II, pp. 113–116, Aug. 2001.; [Publication 4]: V. Karanko and M. Honkala. A parallel harmonic balance simulator for shared memory multicomputers. Proceedings of the 34th European Microwave Conference, pp. 849–851, 2004.; [Publication 5]: M. Honkala and V. Karanko. Mixed preconditioners for harmonic balance Jacobians. International Journal of RF and Microwave Computer-Aided Engineering, vol. 19, no. 2, pp. 211–217, 2009.; [Publication 6]: M. Honkala, V. Karanko, J. Roos, and M. Valtonen. Frequency/time block preconditioners for harmonic balance Jacobians. Proceedings of European Conference on Circuit Theory and Design, pp. 607–610, Aug. 2009.; [Publication 7]: P. Miettinen, M. Honkala, J. Roos, C. Neff, and A. Basermann. Study and development of an efficient RC-in–RC-out MOR method. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, pp. 1277–1280, Aug. 2008.; [Publication 8]: M. Honkala, P. Miettinen, J. Roos, and C. Neff. Hierarchical modelorder reduction flow. Mathematics in Industry 14: Scientific Computing in Electrical Engineering SCEE 2008, (J. Roos and L. R. J. Costa, eds.), pp. 539–546, 2010.; [Publication 9]: J. Roos, M. Honkala, and P. Miettinen. GABOR: global-approximationbased order reduction. Mathematics in Industry 14: Scientific Computing in Electrical Engineering SCEE 2008, (J. Roos and L. R. J. Costa, eds.), pp. 517–514, 2010.; [Publication 10]: P. Miettinen, M. Honkala, J. Roos, and M. Valtonen. PartMOR: partitioningbased realizable model-order reduction method for RLC circuits. IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 3, pp. 374–387, 2011.; 1799-4942 (electronic); 1799-4934 (printed); 1799-4934 (ISSN-L); https://aaltodoc.aalto.fi/handle/123456789/7514; URN:ISBN:978-952-60-4923-6

الاتاحة: https://aaltodoc.aalto.fi/handle/123456789/7514

المؤلفون: Miettinen, Pekka

المساهمون: Roos, Janne, Honkala, Mikko, Sähkötekniikan korkeakoulu, School of Electrical Engineering, Elektroniikan, tietoliikenteen ja automaation tiedekunta, Valtonen, Martti, Aalto-yliopisto, Aalto University

مصطلحات موضوعية: circuit simulation, interconnect modeling, model-order reduction, hierarchical analysis, circuit partitioning, RLC, RC, RL, PartMOR, piirisimulointi, sähköisten kytkentöjen mallinnus, malliredusointi, hierarkinen analyysi, piirijako

وصف الملف: [13] + 29 s. + liitt. 40

Relation: https://aaltodoc.aalto.fi/handle/123456789/106740; URN:NBN:fi:aalto-202104156030

الاتاحة: https://aaltodoc.aalto.fi/handle/123456789/106740

المؤلفون: Palenius, Timo

المساهمون: Roos, Janne, Teknillinen korkeakoulu, Helsinki University of Technology, Sähkö- ja tietoliikennetekniikan osasto, Valtonen, Martti, Aalto-yliopisto, Aalto University

مصطلحات موضوعية: circuit simulation, interconnect simulation, model-order reduction, frequency-domain model, transient analysis, APLAC, piirisimulointi, interconnect-simulointi, malliredusointi, taajuusalueen malli, transienttianalyysi

Relation: https://aaltodoc.aalto.fi/handle/123456789/106398; URN:NBN:fi:aalto-202104155688

الاتاحة: https://aaltodoc.aalto.fi/handle/123456789/106398

المؤلفون: Aaltonen, Sakari

المساهمون: Roos, Janne, Teknillinen korkeakoulu, Helsinki University of Technology, Sähkö- ja tietoliikennetekniikan osasto, Valtonen, Martti, Aalto-yliopisto, Aalto University

مصطلحات موضوعية: circuit simulation, interconnect, order reduction, piirisimulointi, liitospiiri, liityntäpiiri, typistäminen, malliredusointi

Relation: https://aaltodoc.aalto.fi/handle/123456789/106326; URN:NBN:fi:aalto-202104155616

الاتاحة: https://aaltodoc.aalto.fi/handle/123456789/106326

المؤلفون: Palenius, Timo

المساهمون: Roos, Janne, Teknillinen korkeakoulu, Helsinki University of Technology, Sähkö- ja tietoliikennetekniikan osasto, Valtonen, Martti, Aalto-yliopisto, Aalto University

مصطلحات موضوعية: circuit simulation, interconnect simulation, model reduction, frequency-domain model, transient analysis, APLAC, piirisimulointi, interconnect-simulointi, malliredusointi, taajuusalueen malli, transienttianalyysi

Relation: https://aaltodoc.aalto.fi/handle/123456789/90237; URN:NBN:fi:aalto-2020120449072

الاتاحة: https://aaltodoc.aalto.fi/handle/123456789/90237