المؤلفون: Elakhras, Ayatallah, Sawhney, Riya, Guerrieri, Andrea, Josipovic, Lana, Ienne, Paolo

المصدر: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

مصطلحات موضوعية: high-level synthesis, dataflow, load-store queue

وصف الملف: application/application/pdf

Relation: info:eu-repo/semantics/altIdentifier/isbn/978-1-4503-9417-8; info:eu-repo/semantics/altIdentifier/wos/001147764100005; http://hdl.handle.net/20.500.11850/601186; urn:isbn:978-1-4503-9417-8

الاتاحة: https://hdl.handle.net/20.500.11850/601186
https://doi.org/10.3929/ethz-b-000601186

المؤلفون: Josipovic, Lana, Brisk, Philip, Ienne, Paolo

المصدر: ACM Transactions on Embedded Computing Systems. 16(5s)

مصطلحات موضوعية: Load-store queue, spatial computing, allocation, dynamic scheduling, Computer Software, Distributed Computing, Computer Hardware, Computer Hardware & Architecture

وصف الملف: application/pdf

URL الوصول: https://escholarship.org/uc/item/3gd9z8jx

المؤلفون: Josipovic, L, Brisk, P, Ienne, P

المصدر: ACM Transactions on Embedded Computing Systems. 16(5s)

مصطلحات موضوعية: Load-store queue, spatial computing, allocation, dynamic scheduling, Computer Hardware & Architecture, Computer Software, Distributed Computing, Computer Hardware

وصف الملف: application/pdf

URL الوصول: https://escholarship.org/uc/item/3gd9z8jx

المؤلفون: Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne

المصدر: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

مصطلحات موضوعية: high-level synthesis, dataflow, load-store queue

وصف الملف: application/application/pdf

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::aba466bde4433889b8d8910737f23636
https://hdl.handle.net/20.500.11850/601186

المؤلفون: Masahiro GOSHIMA, Naruki KURATA, Ryota SHIOYA, Shuichi SAKAI

المصدر: IEICE Transactions on Electronics. 2015, E98.C(7):580

المؤلفون: Dan Nicolaescu, Alex Veidenbaum, Alex Nicolau

المساهمون: The Pennsylvania State University CiteSeerX Archives

المصدر: http://www.ics.uci.edu/~alexv/Papers/islped03.pdf.

مصطلحات موضوعية: C.1.1 [Processor Architecture, Load/Store Queue, Cache General Terms Design, Performance Keywords low power, low energy, memory, cache, LSQ, load queue, store

وصف الملف: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.61.6901; http://www.ics.uci.edu/~alexv/Papers/islped03.pdf

الاتاحة: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.61.6901
http://www.ics.uci.edu/~alexv/Papers/islped03.pdf

المؤلفون: Ruíz Ramírez, Abraham Josafat

المساهمون: Cristal Kestelman, Adrián

المصدر: UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname

مصطلحات موضوعية: Execució fora d'ordre, memòria Disambiguation, Botiga-de càrrega de reenviament de dades, Store-to-Load Data Forwarding, Informàtica [Àrees temàtiques de la UPC], Out-of-Order Execution, arquitectura del processador, Multiprocessors, Processor Architecture, Load/Store Queue, Multiprocessadors, Memory Disambiguation, Load / Store cua

وصف الملف: application/pdf

URL الوصول: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::b6219e6cc865414702b38cceeca3247d
http://hdl.handle.net/2117/82954

المؤلفون: Jaleel, Aamer, Jacob, Bruce

مصطلحات موضوعية: processor performance, cache behavior, virtual load/store queue (VLSQ)

وصف الملف: 260114 bytes; application/pdf

Relation: A. James Clark School of Engineering; Electrical & Computer Engineering; Digital Repository at the University of Maryland; University of Maryland (College Park, MD); "Using Virtual Load/Store Queues (VLSQs) to reduce the negative effects of reordered memory instructions." Aamer Jaleel and Bruce Jacob. Proc. 11th International Symposium on High Performance Computer Architecture (HPCA 2005), pp. 191-200. San Francisco CA, February 2005.; http://hdl.handle.net/1903/7457

الاتاحة: http://hdl.handle.net/1903/7457

المؤلفون: Zhang, Zhen-Hao, Wang, Xiao-Yin, Tong, Dong, Yi, Jiang-Fang, Lu, Jun-Lin, Wang, Ke-Yi

المساهمون: Wang, XY (reprint author), Peking Univ, Microprocessor Res & Dev Ctr, Beijing 100871, Peoples R China., Peking Univ, Microprocessor Res & Dev Ctr, Beijing 100871, Peoples R China., Minist Educ, Engn Res Ctr Microprocessor & Syst, Beijing 100871, Peoples R China., Peking Univ, Sch Elect Engn & Comp Sci, Beijing 100871, Peoples R China.

المصدر: SCI

مصطلحات موضوعية: store-load forwarding, load/store queue, value-based load re-execution, MEMORY, QUEUE, PROCESSORS

Relation: JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY.2012,27,(4),769-780.; 873254; http://hdl.handle.net/20.500.11897/393170; WOS:000306410600011

الاتاحة: https://hdl.handle.net/20.500.11897/393170
https://doi.org/10.1007/s11390-012-1263-7

المؤلفون: 吳東樺

مصطلحات موضوعية: 載入儲存佇列, 功率消耗, LSQ, Load Store Queue, Energy-efficiency, CAM

وصف الملف: 143 bytes; text/html

Relation: http://ir.lib.ntust.edu.tw/handle/987654321/15701; http://ir.lib.ntust.edu.tw/bitstream/987654321/15701/1/index.html

الاتاحة: http://ir.lib.ntust.edu.tw/handle/987654321/15701
http://ir.lib.ntust.edu.tw/bitstream/987654321/15701/1/index.html

المؤلفون: Bhattacharyya, Atri, Ienne, Paolo

مصطلحات موضوعية: Automated synthesis, Automated LSQ allocation, architecture, synthesis, load store queue, LSQ, elastic circuit, Optimize circuit, high level synthesis, FPGA

URL الوصول: https://explore.openaire.eu/search/publication?articleId=od_______185::60824c6c9f71ab80ee92feec76ef262e
https://infoscience.epfl.ch/record/261327

المؤلفون: Cristal Kestelman, Adrián, Ruíz Ramírez, Abraham Josafat

مصطلحات الفهرس: Àrees temàtiques de la UPC::Informàtica, Multiprocessors, arquitectura del processador, Load / Store cua, Execució fora d'ordre, memòria Disambiguation, Botiga-de càrrega de reenviament de dades, Processor Architecture, Load/Store Queue, Out-of-Order Execution, Memory Disambiguation, Store-to-Load Data Forwarding, Multiprocessadors, Master thesis

URL: http://hdl.handle.net/2117/82954