المؤلفون: Ricardo M. F. Martins, Nuno C. C. Lourenco

المصدر: IEEE Access, Vol 11, Pp 35965-35983 (2023)

مصطلحات موضوعية: Analog and radio-frequency, automatic routing, layout-aware synthesis, machine learning, parasitic-inclusive synthesis, path-finding algorithm, Electrical engineering. Electronics. Nuclear engineering, TK1-9971

وصف الملف: electronic resource

Relation: https://ieeexplore.ieee.org/document/10097479/; https://doaj.org/toc/2169-3536

URL الوصول: https://doaj.org/article/d8a35d3af4634c6a80f4c79f37d77262

المؤلفون: Castro López, Rafael, Fernández Fernández, Francisco Vidal, Rodríguez Vázquez, Ángel Benito

المساهمون: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo

مصطلحات موضوعية: Physical Synthesis, Design Reuse, Layout-Aware Synthesis, Procedural Layout Generation

Relation: VLSI Circuits and Systems II (2005), p 661-672; TEC2004-01752; http://dx.doi.org/10.1117/12.607932; https://idus.us.es/handle//11441/92228

الاتاحة: https://idus.us.es/handle//11441/92228

المؤلفون: Castro López, Rafael, Fernández Fernández, Francisco Vidal, Rodríguez Vázquez, Ángel Benito

المساهمون: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo

مصطلحات موضوعية: Analog CAD, Floorplan Sizing, Layout Parasitics, Layout Templates, Layout-Aware Synthesis

Relation: VLSI Circuits and Systems II (2005), p 673-684; TEC2004-01752; http://dx.doi.org/10.1117/12.607933; https://idus.us.es/handle//11441/92294

الاتاحة: https://idus.us.es/handle//11441/92294

المؤلفون: Ratkovic, Ivan, Palomar Pérez, Óscar, Stanic, Milan, Unsal, Osman Sabri, Cristal Kestelman, Adrián, Valero Cortés, Mateo

المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions

مصطلحات موضوعية: Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència, Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics, Power electronics, Integrated circuits, Adder, Design space exploration, Estimation method, Low-power, Physical layout aware synthesis, Place and route, Electrònica de potència, Circuits integrats

وصف الملف: 6 p.

Relation: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6903346; Ratkovic, I. [et al.]. Physical vs. physically-aware estimation flow: case study of design space exploration of adders. A: IEEE Computer Society Annual Symposium on VLSI. "ISVLSI 2014: 2014 IEEE Computer Society Annual Symposium on VLSI: 9-11 July 2014: Tampa, Florida". Tampa: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 118-123.; http://hdl.handle.net/2117/24800

الاتاحة: http://hdl.handle.net/2117/24800
https://doi.org/10.1109/ISVLSI.2014.14

المؤلفون: AGARWAL, ANURADHA

المصدر: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454.

مصطلحات موضوعية: Analog, Radio-frequency, Circuit Synthesis, Layout Parasitics, Performance Modeling, Parasitic Estimation and Modeling, Layout-Aware Synthesis, Circuit sizing, Parasitic Corners, Yield Optimization, Parasitic Capacitances, Dynamic Performance Macromodel

Relation: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

الاتاحة: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

المؤلفون: Castro López, Rafael, Fernández Fernández, Francisco Vidal, Rodríguez Vázquez, Ángel Benito

المساهمون: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo

المصدر: idUS. Depósito de Investigación de la Universidad de Sevilla
instname

مصطلحات موضوعية: Layout Parasitics, Layout Templates, Floorplan Sizing, Hardware_INTEGRATEDCIRCUITS, Layout-Aware Synthesis, Analog CAD

وصف الملف: application/pdf

URL الوصول: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::855af95a07ec93600887eaa09b9c2c04

المؤلفون: Castro López, Rafael, Fernández Fernández, Francisco Vidal, Rodríguez Vázquez, Ángel Benito

المساهمون: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo

المصدر: idUS. Depósito de Investigación de la Universidad de Sevilla
instname

مصطلحات موضوعية: Procedural Layout Generation, Hardware_INTEGRATEDCIRCUITS, Design Reuse, Physical Synthesis, Layout-Aware Synthesis

وصف الملف: application/pdf

URL الوصول: https://explore.openaire.eu/search/publication?articleId=RECOLECTA___::1e552880c7f5d7cfa7807aa170391281

المؤلفون: Krishnan, Vyas

المصدر: USF Tampa Graduate Theses and Dissertations

مصطلحات موضوعية: behavioral synthesis, power-aware design, thermal analysis, interconnectcentric design, stochastic interconnect estimation, layout-aware synthesis, American Studies, Arts and Humanities

وصف الملف: application/pdf

Relation: https://digitalcommons.usf.edu/etd/347; https://digitalcommons.usf.edu/context/etd/article/1346/viewcontent/SFE0002785.pdf

الاتاحة: https://digitalcommons.usf.edu/etd/347
https://digitalcommons.usf.edu/context/etd/article/1346/viewcontent/SFE0002785.pdf

المؤلفون: Krishnan, Vyas

المصدر: Graduate Theses and Dissertations.

مصطلحات موضوعية: behavioral synthesis, power-aware design, thermal analysis, interconnectcentric design, stochastic interconnect estimation, layout-aware synthesis, American Studies, Arts and Humanities

وصف الملف: application/pdf

الاتاحة: https://scholarcommons.usf.edu/etd/347
https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=1346&context=etd

المؤلفون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions, Ratkovic, Ivan, Palomar Pérez, Óscar, Stanic, Milan, Unsal, Osman Sabri, Cristal Kestelman, Adrián, Valero Cortés, Mateo

مصطلحات الفهرس: Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència, Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics, Power electronics, Integrated circuits, Adder, Design space exploration, Estimation method, Low-power, Physical layout aware synthesis, Place and route, Electrònica de potència, Circuits integrats, Conference report

URL: http://hdl.handle.net/2117/24800
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6903346
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6903346

المؤلفون: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo, Castro López, Rafael, Fernández Fernández, Francisco Vidal, Rodríguez Vázquez, Ángel Benito

مصطلحات الفهرس: Physical Synthesis, Design Reuse, Layout-Aware Synthesis, Procedural Layout Generation, info:eu-repo/semantics/conferenceObject

URL: VLSI Circuits and Systems II (2005), p 661-672
TEC2004-01752
http://dx.doi.org/10.1117/12.607932

المؤلفون: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo, Castro López, Rafael, Fernández Fernández, Francisco Vidal, Rodríguez Vázquez, Ángel Benito

مصطلحات الفهرس: Analog CAD, Floorplan Sizing, Layout Parasitics, Layout Templates, Layout-Aware Synthesis, info:eu-repo/semantics/conferenceObject

URL: VLSI Circuits and Systems II (2005), p 673-684
TEC2004-01752
http://dx.doi.org/10.1117/12.607933