المؤلفون: Veera Manikanth, Mukkapati, Prasad, Kanakala Manikanta

المصدر: International Journal of Innovative Technology and Research; Vol 5, No 3 (2017): April - May 2017; 6305-6308

مصطلحات موضوعية: ECE, Binary Decision Diagram Applications, Energy Efficiency, Hybrid-CMOS Logic Style, Systematic Design Methodology, Three-Input XOR/XNOR Circuits

وصف الملف: application/pdf

Relation: http://www.ijitr.com/index.php/ojs/article/view/1722/pdf; http://www.ijitr.com/index.php/ojs/article/view/1722

الاتاحة: http://www.ijitr.com/index.php/ojs/article/view/1722

المؤلفون: Karmani, Mouna, Khedhiri, Chiraz, Hamdi, Belgacem, Rahmani, Amir-Mohammad, Man, Ka, Lok, Wan, Kaiyu

المساهمون: Université de Monastir - University of Monastir (UM), University of Turku, Xi'an Jiaotong-Liverpool University Suzhou, James J. Park, Albert Zomaya, Sang-Soo Yeo, Sartaj Sahni, TC 10, WG 10.3

المصدر: Lecture Notes in Computer Science ; 9th International Conference on Network and Parallel Computing (NPC) ; https://inria.hal.science/hal-01551326 ; 9th International Conference on Network and Parallel Computing (NPC), Sep 2012, Gwangju, South Korea. pp.516-523, ⟨10.1007/978-3-642-35606-3_61⟩

مصطلحات موضوعية: XOR-XNOR circuits, Concurrent Error Detection, fault-secure property, self-testing property, fault model, [INFO]Computer Science [cs]

جغرافية الموضوع: Gwangju, South Korea

Relation: hal-01551326; https://inria.hal.science/hal-01551326; https://inria.hal.science/hal-01551326/document; https://inria.hal.science/hal-01551326/file/978-3-642-35606-3_61_Chapter.pdf

الاتاحة: https://inria.hal.science/hal-01551326
https://inria.hal.science/hal-01551326/document
https://inria.hal.science/hal-01551326/file/978-3-642-35606-3_61_Chapter.pdf
https://doi.org/10.1007/978-3-642-35606-3_61

المؤلفون: Chiraz Khedhiri, Kaiyu Wan, Amir-Mohammad Rahmani, Mouna Karmani, Belgacem Hamdi, Ka Lok Man

المساهمون: Université de Monastir - University of Monastir (UM), University of Turku, Xi'an Jiaotong-Liverpool University [Suzhou], James J. Park, Albert Zomaya, Sang-Soo Yeo, Sartaj Sahni, TC 10, WG 10.3

المصدر: Lecture Notes in Computer Science
9th International Conference on Network and Parallel Computing (NPC)
9th International Conference on Network and Parallel Computing (NPC), Sep 2012, Gwangju, South Korea. pp.516-523, ⟨10.1007/978-3-642-35606-3_61⟩
Lecture Notes in Computer Science ISBN: 9783642356056
NPC

مصطلحات موضوعية: fault-secure property, Computer science, 020208 electrical & electronic engineering, Logic family, 02 engineering and technology, Circuit extraction, 020202 computer hardware & architecture, Arithmetic logic unit, Logic synthesis, fault model, Concurrent Error Detection, XOR-XNOR circuits, Logic gate, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Arithmetic, Hardware_ARITHMETICANDLOGICSTRUCTURES, self-testing property, Asynchronous circuit, Logic optimization, Register-transfer level

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e878bff95e45ce8477492523344099ef
https://hal.inria.fr/hal-01551326/file/978-3-642-35606-3_61_Chapter.pdf

المؤلفون: Mohamed Elgamel, Sumeer Goel, Magdy Bayoumi

المساهمون: The Pennsylvania State University CiteSeerX Archives

المصدر: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/glsvlsi03/pdffiles/p2_15.pdf.

مصطلحات موضوعية: nanometer technology, Noise tolerant, XOR-XNOR circuits, multipliers

وصف الملف: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.536.3261; http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/glsvlsi03/pdffiles/p2_15.pdf

الاتاحة: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.536.3261
http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/glsvlsi03/pdffiles/p2_15.pdf

المؤلفون: 林依俊, Yi-Jyun Lin

المساهمون: 資訊科學與工程學系, 張延任

مصطلحات موضوعية: 栓鎖(Latch), 雙邊緣觸發正反器(Dual Edge Triggered Flip Flop), 脈衝觸發(Pulse Triggered), 競爭條件(Race Condition), XOR/XNOR電路設計(XOR/XNOR Circuits Design), Latch, Dual Edge Triggered Flip Flop, Pulse Triggered, XOR/XNOR Circuits Design, Race Condition

Relation: http://hdl.handle.net/11455/98207

الاتاحة: http://hdl.handle.net/11455/98207