يعرض 1 - 20 نتائج من 209 نتيجة بحث عن '"Wunderlich, H.-J."', وقت الاستعلام: 0.57s تنقيح النتائج
  1. 1
    Conference
    System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults

    المؤلفون: Kochte, M. A., Zoellin, C. G., Baranowski, R., Imhof, M. E., Wunderlich, H. J., Hatami, N., DI CARLO, STEFANO, PRINETTO, Paolo Ernesto

    المساهمون: Kochte, M. A., Zoellin, C. G., Baranowski, R., Imhof, M. E., Wunderlich, H. J., Hatami, N., DI CARLO, Stefano, Prinetto, Paolo Ernesto

    مصطلحات موضوعية: DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, circuit reliability, fault simulation, concurrent multi-level simulation

    وصف الملف: ELETTRONICO

    Relation: info:eu-repo/semantics/altIdentifier/isbn/9781424472062; info:eu-repo/semantics/altIdentifier/wos/WOS:000287978200102; ispartofbook:Titolo volume non avvalorato; IEEE International Test Conference (ITC); numberofpages:1; http://hdl.handle.net/11583/2380374; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-79951640907; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5699309

    الاتاحة: http://hdl.handle.net/11583/2380374
    https://doi.org/10.1109/TEST.2010.5699309
    http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5699309

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  2. 2
    Conference
    Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

    المؤلفون: Kochte, M. A., Zoellin, C. G., Baranowski, R., Imhof, M. E., Wunderlich, H. J., Hatami, N., DI CARLO, STEFANO, PRINETTO, Paolo Ernesto

    المساهمون: Kochte, M. A., Zoellin, C. G., Baranowski, R., Imhof, M. E., Wunderlich, H. J., Hatami, N., DI CARLO, Stefano, Prinetto, Paolo Ernesto

    مصطلحات موضوعية: DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, Circuit fault, Integrated circuit modeling, Logic gate, Object oriented modeling, Time domain analysi, Time varying systems

    وصف الملف: STAMPA

    Relation: info:eu-repo/semantics/altIdentifier/isbn/9781424488414; info:eu-repo/semantics/altIdentifier/wos/WOS:000407126900001; ispartofbook:Titolo volume non avvalorato; IEEE 19th Asian Test Symposium (ATS); firstpage:3; lastpage:8; numberofpages:6; http://hdl.handle.net/11583/2380373; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-79951608265; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5692211

    الاتاحة: http://hdl.handle.net/11583/2380373
    https://doi.org/10.1109/ATS.2010.10
    http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5692211

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  3. 3
    Conference
    Test exploration and validation using transaction level models

    المؤلفون: Kochte, M. A, Zollen, C. G, Imhof, M. E, Khaligh, R. S, Radetzki, M., Wunderlich, H. J, DI CARLO, STEFANO, PRINETTO, Paolo Ernesto

    المساهمون: Kochte, M. A, Zollen, C. G, Imhof, M. E, Khaligh, R. S, Radetzki, M., Wunderlich, H. J, DI CARLO, Stefano, Prinetto, Paolo Ernesto

    مصطلحات موضوعية: DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, Automatic testing, Computational modeling, Concurrent computing, Context modeling, Design for testability, Discrete event simulation, Object oriented modeling, Scheduling, System testing

    وصف الملف: STAMPA

    Relation: info:eu-repo/semantics/altIdentifier/isbn/9781424437818; info:eu-repo/semantics/altIdentifier/wos/WOS:000273246700224; ispartofbook:Design, Automation and Test in Europe, Conference and Exhibition (DATE); DATE '09 : Design, Automation & Test in Europe Conference & Exhibition, 2009; firstpage:1250; lastpage:1253; numberofpages:4; http://hdl.handle.net/11583/2281242; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-70350077794; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5090856

    الاتاحة: http://hdl.handle.net/11583/2281242
    https://doi.org/10.1109/DATE.2009.5090856
    http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5090856

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  4. 4
    Conference
    Digital, memory and mixed-signal test engineering education: five centres of competence in Europe

    المؤلفون: Flottes M. L, Bertrand Y., Balado L., Lupon E., Biasizzo A., Novak F., Pricopi N., Wunderlich H. J., DI CARLO, STEFANO, PRINETTO, Paolo Ernesto

    المساهمون: Flottes, M. L., Bertrand, Y., Balado, L., Lupon, E., Biasizzo, A., Novak, F., DI CARLO, Stefano, Prinetto, Paolo Ernesto, Pricopi, N., Wunderlich, H. J.

    مصطلحات موضوعية: DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, Circuit testing, Continuing education, Design engineering, Electronic equipment testing, Engineering education, Industrial training, Integrated circuit testing, automatic test equipment

    وصف الملف: STAMPA

    Relation: info:eu-repo/semantics/altIdentifier/isbn/0769520812; info:eu-repo/semantics/altIdentifier/wos/WOS:000189390400022; ispartofbook:Titolo volume non avvalorato; IEEE 2nd International Workshop on Electronic Design, Test and Applications (DELTA); firstpage:135; lastpage:139; numberofpages:5; http://hdl.handle.net/11583/1499949; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-4544286355; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1409829

    الاتاحة: http://hdl.handle.net/11583/1499949
    https://doi.org/10.1109/DELTA.2004.10024
    http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1409829

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  5. 5
    Conference
    Test engineering education in Europe: the EuNICE-Test project

    المؤلفون: Bertrand Y., Flottes M. L, Balado L., Figueras J., Biasizzo A., Novak F., Pricopi N., Wunderlich H. J., Van Der Heyden J. P., DI CARLO, STEFANO, PRINETTO, Paolo Ernesto

    المساهمون: Bertrand, Y., Flottes, M. L., Balado, L., Figueras, J., Biasizzo, A., Novak, F., DI CARLO, Stefano, Prinetto, Paolo Ernesto, Pricopi, N., Wunderlich, H. J., Van Der Heyden, J. P.

    مصطلحات موضوعية: DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, Continuing education, Engineering education, Industrial training, Microelectronic, Test facilitie, Testing

    وصف الملف: STAMPA

    Relation: info:eu-repo/semantics/altIdentifier/isbn/0769519733; info:eu-repo/semantics/altIdentifier/wos/WOS:000183433900039; ispartofbook:Titolo volume non avvalorato; IEEE International Conference on Microelectronic Systems Education (ICMSE); firstpage:85; lastpage:86; numberofpages:2; http://hdl.handle.net/11583/1499946; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-21444443748; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1205266

    الاتاحة: http://hdl.handle.net/11583/1499946
    https://doi.org/10.1109/MSE.2003.1205266
    http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1205266

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  6. 6
    Conference
    On applying the set covering model to reseeding

    المؤلفون: CHIUSANO, SILVIA ANNA, DI CARLO, STEFANO, PRINETTO, Paolo Ernesto, WUNDERLICH H. J.

    المساهمون: Chiusano, SILVIA ANNA, DI CARLO, Stefano, Prinetto, Paolo Ernesto, Wunderlich, H. J.

    مصطلحات موضوعية: DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, Built-in self-test, Circuit testing, System testing

    وصف الملف: STAMPA

    Relation: info:eu-repo/semantics/altIdentifier/isbn/0769509932; info:eu-repo/semantics/altIdentifier/wos/WOS:000168322500026; ispartofbook:Titolo volume non avvalorato; Design, Automation and Test in Europe, Conference and Exhibition (DATE); firstpage:156; lastpage:160; numberofpages:5; http://hdl.handle.net/11583/1416287; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-0009022223; http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=915017

    الاتاحة: http://hdl.handle.net/11583/1416287
    https://doi.org/10.1109/DATE.2001.915017
    http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=915017

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  7. 7
    Academic Journal
    Transparent Structural Online Test for Reconfigurable Systems

    المؤلفون: Abdelfattah, M., Bauer, L., Braun, C., Imhof, M. E., Kochte, M. A., Zhang, H., Henkel, J., Wunderlich, H.-J.

    مصطلحات موضوعية: ddc:004, DATA processing & computer science, info:eu-repo/classification/ddc/004

    Relation: info:eu-repo/semantics/altIdentifier/isbn/978-1-4673-2082-5; https://publikationen.bibliothek.kit.edu/1000032725

    الاتاحة: https://publikationen.bibliothek.kit.edu/1000032725

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  8. 8
    Academic Journal
    Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults

    المؤلفون: Baranowski, R., Hatami, N., Imhof, M. E., Kochte, M., Wunderlich, H. J., Zoellin, C. G., DI CARLO, STEFANO, PRINETTO, Paolo Ernesto

    المساهمون: Baranowski, R., DI CARLO, Stefano, Hatami, N., Imhof, M. E., Kochte, M., Prinetto, Paolo Ernesto, Wunderlich, H. J., Zoellin, C. G.

    مصطلحات موضوعية: fault simulation, multi-level, transaction-level modeling, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, testing, reliability

    وصف الملف: STAMPA

    Relation: info:eu-repo/semantics/altIdentifier/wos/WOS:000293465200002; volume:54; issue:9; firstpage:1784; lastpage:1796; numberofpages:13; journal:SCIENCE CHINA. INFORMATION SCIENCES; http://hdl.handle.net/11583/2426393; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-79961082195; http://www.springerlink.com/content/538081568x71808r/fulltext.pdf

    الاتاحة: http://hdl.handle.net/11583/2426393
    https://doi.org/10.1007/s11432-011-4366-9
    http://www.springerlink.com/content/538081568x71808r/fulltext.pdf

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  9. 9
    Book
    Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms

    المؤلفون: Yarmolik, V. N., Bykov, I. V., Hellebrand, S., Wunderlich, H.-J.

    المصدر: Lecture Notes in Computer Science ; Dependable Computing — EDCC-3 ; page 339-348 ; ISSN 0302-9743 ; ISBN 9783540664833 9783540482543

    الاتاحة: https://doi.org/10.1007/3-540-48254-7_23
    http://link.springer.com/content/pdf/10.1007/3-540-48254-7_23

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  10. 10
    Conference
    Synthesis of IDDQ-Testable Circuits: Integrating Built-in Current Sensors

    المؤلفون: Wunderlich, H J, Herzog, M, Figueras Pàmies, Joan, Carrasco, Juan A., Calderón, A

    المساهمون: Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat

    مصطلحات موضوعية: Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics, Integrated circuits, Circuits integrats

    وصف الملف: 8 p.

    Relation: Wunderlich, H. [et al.]. Synthesis of IDDQ-testable circuits: integrating built-in current sensors. A: IEEE European Design and Automation Conf. "Proc. IEEE European Design and Automation Conf.". 1995, p. 573-580.; http://hdl.handle.net/2117/20064

    الاتاحة: http://hdl.handle.net/2117/20064

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  11. 11
    Electronic Resource
    Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch

    المؤلفون: Kyushu Institute of Technology, Iizuka, 820-8502, Japan, University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany, Advanced Micro Devices, Inc., Sunnyvale, CA 94088, USA, Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M. A., Schneider, E., Wunderlich, H.-J., Qian, J.

    مصطلحات الفهرس: launch switching activity, IR-drop, logic path, clock path, false capture failure, test clock stretch, X-filling, 548, Journal Article, AM

    URL: http://hdl.handle.net/10228/00007585
    https://kyutech.repo.nii.ac.jp/?action=repository_action_common_download&item_id=6375&item_no=1&attribute_id=17&file_no=1
    https://doi.org/10.1109/ATS.2015.25
    9781467397391
    https://doi.org/10.1109/ATS.2015.25

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  12. 12
    Conference
    Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene

    المؤلفون: Kochte, M. A., Zoellin, C. G., Baranowski, R., Imhof, M. E., Wunderlich, H. J., Hatami, N., DI CARLO, STEFANO, PRINETTO, Paolo Ernesto

    المساهمون: Kochte, M. A., Zoellin, C. G., Baranowski, R., Imhof, M. E., Wunderlich, H. J., Hatami, N., DI CARLO, Stefano, Prinetto, Paolo Ernesto

    وصف الملف: ELETTRONICO

    Relation: info:eu-repo/semantics/altIdentifier/isbn/9783800732999; ispartofbook:GMM/GI/ITG-Fachtagung; Zuverlässigkeit und Entwurf (GMM-FB 66); volume:13. bis 15; firstpage:25; lastpage:32; numberofpages:8; http://hdl.handle.net/11583/2380372; http://www.vde-verlag.de/proceedings-de/453299003.html

    الاتاحة: http://hdl.handle.net/11583/2380372
    http://www.vde-verlag.de/proceedings-de/453299003.html

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  13. 13
    Academic Journal
    On-Line Prediction of NBTI-induced Aging Rates

    المؤلفون: Baranowski, R., Firouzi, F., Kiamehr, S., Chang Liu, Tahoori, M. B., Wunderlich, H.-J.

    المصدر: ISSN: 1530-1591.

    مصطلحات موضوعية: ddc:004, DATA processing & computer science, info:eu-repo/classification/ddc/004

    Relation: Proceedings -Design, Automation and Test in Europe, DATE; info:eu-repo/semantics/altIdentifier/isbn/978-1-4799-6404-8; info:eu-repo/semantics/altIdentifier/issn/1530-1591; https://publikationen.bibliothek.kit.edu/1000052481

    الاتاحة: https://publikationen.bibliothek.kit.edu/1000052481

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  14. 14
    Academic Journal
    GUARD: GUAranteed reliability in dynamically reconfigurable systems

    المؤلفون: Zhang, H., Kochte, M. A., Imhof, M. E., Bauer, L., Wunderlich, H.-J., Henkel, J.

    مصطلحات موضوعية: ddc:004, DATA processing & computer science, info:eu-repo/classification/ddc/004

    Relation: info:eu-repo/semantics/altIdentifier/isbn/978-1-4503-2730-5; https://publikationen.bibliothek.kit.edu/1000046263

    الاتاحة: https://publikationen.bibliothek.kit.edu/1000046263

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  15. 15
    Conference
    GUARD ; GUAranteed Reliability in Dynamically Reconfigurable Systems

    المؤلفون: Zhang, Hongyan, Kochte, Michael A., Imhof, Michael E., Bauer, Lars, Wunderlich, H.-J., Henkel, Jörg

    المصدر: Proceedings of the 51st Annual Design Automation Conference

    الاتاحة: http://dx.doi.org/10.1145/2593069.2593146
    https://dl.acm.org/doi/pdf/10.1145/2593069.2593146

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  16. 16
    Academic Journal
    Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures

    المؤلفون: Zhang, H., Bauer, L., Kochte, M. A., Schneider, E., Braun, C., Imhof, M. E., Wunderlich, H.-J., Henkel, J.

    مصطلحات موضوعية: ddc:004, DATA processing & computer science, info:eu-repo/classification/ddc/004

    Relation: info:eu-repo/semantics/altIdentifier/isbn/978-1-47-990860-8; https://publikationen.bibliothek.kit.edu/1000038859

    الاتاحة: https://publikationen.bibliothek.kit.edu/1000038859

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  17. 17
    Conference
    A pseudo-dynamic comparator for error detection in fault tolerant architectures

    المؤلفون: Tran, D. A., Virazel, A., Bosio, A., Dilillo, L., Girard, P., Todri, A., Imhof, M. E., Wunderlich, H.-J.

    المصدر: 2012 IEEE 30th VLSI Test Symposium (VTS) ; volume 28, page 50-55

    الاتاحة: http://dx.doi.org/10.1109/vts.2012.6231079
    http://xplorestaging.ieee.org/ielx5/6222548/6231057/06231079.pdf?arnumber=6231079

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  18. 18
    Conference
    Variation-Aware Fault Grading

    المؤلفون: Czutro, A., Imhof, M.E., Jiang, J., Mumtaz, A., Sauer, M., Becker, B., Polian, I., Wunderlich, H.-J.

    المصدر: 2012 IEEE 21st Asian Test Symposium ; page 344-349

    الاتاحة: http://dx.doi.org/10.1109/ats.2012.14
    http://xplorestaging.ieee.org/ielx5/6392591/6394156/06394227.pdf?arnumber=6394227

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  19. 19
    Conference
    Non-intrusive BIST for systems-on-a-chip

    المؤلفون: CHIUSANO, SILVIA ANNA, PRINETTO, Paolo Ernesto, WUNDERLICH H. J.

    المساهمون: Chiusano, SILVIA ANNA, Prinetto, Paolo Ernesto, Wunderlich, H. J.

    وصف الملف: STAMPA

    Relation: info:eu-repo/semantics/altIdentifier/isbn/0780365461; info:eu-repo/semantics/altIdentifier/wos/WOS:000166038000076; ispartofbook:Titolo volume non avvalorato; IEEE International Test Conference; firstpage:644; lastpage:651; numberofpages:8; http://hdl.handle.net/11583/1408845; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-0034476674

    الاتاحة: http://hdl.handle.net/11583/1408845

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  20. 20
    Conference
    Optimal Hardware Pattern Generation for Functional BIST

    المؤلفون: CATALDO S., WUNDERLICH H. J., CHIUSANO, SILVIA ANNA, PRINETTO, Paolo Ernesto

    المساهمون: Cataldo, S., Chiusano, SILVIA ANNA, Prinetto, Paolo Ernesto, Wunderlich, H. J.

    Relation: info:eu-repo/semantics/altIdentifier/isbn/9780769505374; ispartofbook:Titolo volume non avvalorato; IEEE Design, Automation and Test in Europe; firstpage:292; lastpage:297; http://hdl.handle.net/11583/1408855; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-3142671162

    الاتاحة: http://hdl.handle.net/11583/1408855

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