يعرض 1 - 20 نتائج من 48 نتيجة بحث عن '"Suh Youseok"', وقت الاستعلام: 0.53s تنقيح النتائج
  1. 1
    Patent
    Memory cell system with multiple nitride layers
    View record in USPTO Patent Grants

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  2. 2
    Patent
    Gate fringing effect based channel formation for semiconductor device
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  3. 3
    Patent
    Self-aligned STI with single poly for manufacturing a flash memory device
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  4. 4
    Patent
    Partial local self boosting for NAND
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  5. 5
    5G and AI Integrated High Performance Mobile SoC Process-Design Co-Development and Production with 7nm EUV FinFET Technology

    المؤلفون: Leo Kim, Yuri Y. Masuoka, Paul Ivan Penzes, Giri Nallapati, Ying Chen, Venu Boynapalli, S. C. Song, Jason Cheng, Lixin Ge, Sung-Won Kim, Chidi Chidambaram, Rajagopal Narayanan, Xiao-Yong Wang, Jihong Choi, Ukjin Roh, Jerry Bao, Hyejun Jin, Byungmoo Song, Deepak Sharma, Gary Chen, Ming Cai, Zhimin Song, Jie Deng, Jin-Kyu Lee, Vicki Lin, Hao Wang, Kwon Lee, Suh Youseok

    المصدر: 2020 IEEE Symposium on VLSI Technology.

    مصطلحات موضوعية: Computer architecture, Computer science, Extreme ultraviolet lithography, Process (computing), Co-development, Technology integration, Production (economics), Process design, Low voltage, 5G

    URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::9b4d7e8ce5ec3791decfa7aff83431a5
    https://doi.org/10.1109/vlsitechnology18217.2020.9265074

    View record in OpenAIRE

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  6. 6
    Patent
    Apparatus and method for extended nitride layer in a flash memory
    View record in USPTO Patent Grants

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  7. 7
    Patent
    Memory cell system with charge trap
    View record in USPTO Patent Grants

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  8. 8
    Patent
    Memory system with protection layer to cover the memory gate stack and methods for forming same
    View record in USPTO Patent Grants

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  9. 9
    Patent
    PARTIAL LOCAL SELF BOOSTING FOR NAND
    View record in USPTO Patent Applications

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  10. 10
    Patent
    3D INTEGRATED CIRCUIT SYSTEM AND METHOD
    View record in USPTO Patent Applications

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  11. 11
    Patent
    APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY
    View record in USPTO Patent Applications

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  12. 12
    Patent
    3-D integrated circuit system and method
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  13. 13
    Patent
    Scaled down select gates of NAND flash memory cell strings and method of forming same
    View record in USPTO Patent Grants

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  14. 14
    Patent
    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
    View record in USPTO Patent Grants

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  15. 15
    Patent
    NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME
    View record in USPTO Patent Applications

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  16. 16
    Patent
    Partial local self-boosting of a memory cell channel
    View record in USPTO Patent Grants

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  17. 17
    Patent
    Memory device with barrier layer
    View record in USPTO Patent Grants

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  18. 18
    Patent
    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
    View record in USPTO Patent Grants

    أضف إلى المفضلة
  19. 19
    Patent
    GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE
    View record in USPTO Patent Applications

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  20. 20
    Patent
    SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME
    View record in USPTO Patent Applications

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