المؤلفون: 廖育德, Liaw, Yu-Te

المساهمون: 李建模, 臺灣大學：電子工程學研究所

مصطلحات موضوعية: 測試資料壓縮, 測試時間壓縮, 系統晶片測試整合, Test data compression, Test time compression, SoC test integration

وصف الملف: 600537 bytes; application/pdf

Relation: [Bayraktaroglu 01] Bayraktaroglu, I., and A. Ogailoglu, “Test Volume and Application Time Reduction through Scan Chain Concealment,” Proc. of Design Automation Conference, pp. 151-155, 2001. [Bayraktaroglu 03] Bayraktaroglu, I., and A. Ogailoglu, “Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression,” Proc. of VLSI Test Symposium, pp.113-118, 2003. [Chandra 00] Chandra, A. and Chakrabarty, K., “Test Data Compression for System-on-a-Chip using Golomb Codes,” VLSI Test Symposium, pp. 113-120, 2000. [Chandra 01] Chandra, A. and Chakrabarty, K., “Efficient Test Data Compression and Decompression for System-on-a-Chip Using Internal Scan Chains and Golomb Coding,” Design, Automation and Test in Europe, pp. 145-149, 2001. [Chandra 03] Chandra, A. and Chakrabarty, K., “Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-length (FDR) Codes,” IEEE Transactions on Computers, Volume: 52, Issue: 8, pp. 1076-1088, 2003. [Das 00] Das, D., and N.A. Touba, “Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns,” Proc. of International Test Conference, pp. 115-122, 2000. [Hamzaoglu 99] Hamzaoglu, I., and J.H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” Proc. of Int. Symposium on Fault Tolerant Computing, pp. 260-267, 1999. [Hellebrand 95a] Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” IEEE Trans. on Computers, Vol. 44, No. 2, pp. 223-233, 1995. [Hellebrand 95b] Hellebrand, S., B. Reeb, S. Tarnick, and H.-J. Wunderlich, “ Pattern Generation for a Deterministic BIST Scheme,” Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 88-94, 1995. [Hsu 01] Hsu, F.F. and Butler, K.M. and Patel, J.H., “A Case Study on the Implementation of the Illinois Scan Architecture,” Test Conference, pp. 538-547, 2001. [Huffman 52] D. A. Huffman, “A Method for the Construction of Minimum Redundancy Codes,” in Proc. IRE, vol. 40, 1952, pp. 1098–1101. [Ichihara 00] Ichihara, H., Kinoshita, K., Pomeranz, I. and Reddy, S.M., “Test Transformation to Improve Compaction by Statistical Encoding,” VLSI Design, pp. 294-299, 2000. [Jas 98] Jas, A. and Touba, N.A., “Test Vector Decompression via Cyclical Scan Chains and its Application to Testing Core-based Designs,” Test Conference, pp. 458-464, 1998. [Jas 99] Jas, A., J. Ghosh-Dastidar, and N.A. Touba, “Scan Vector Compression/Decompression Using Statistical Coding,” Proc. of IEEE VLSI Test Symposium, pp. 114-120, 1999. [Jas 00] Jas, A., B. Pouya, and N.A. Touba, “Virtual Scan Chains: A Means for Reducing Scan Length in Cores,” Proc. of VLSI Test Symposium, pp. 73-78, 2000. [Konemann 91] Konemann, B., “LFSR-Coded Test Patterns for Scan Designs,” Proc. of European Test Conf., pp. 237-242, 1991. [Konemann 01] Konemann, B., “A SmartBIST Variant with Guaranteed Encoding,” Proc. of Asian Test Symposium, pp. 325-330, 2001. [Krishna 01] Krishna, C.V., A. Jas, and N.A. Touba, “Test Vector Encoding Using Partial LFSR Reseeding,” Proc. of IEEE International Test Conference, pp. 885-893, 2001. [Krishna 02] Krishna, C.V., and N.A. Touba, “Reducing Test Data Volume Using LFSR Reseeding with Seed Compression,” Proc. of IEEE International Test Conference, pp. 321-330, 2001. [Krishna 03] Krishna, C.V. and Touba, N.A., “Adjustable Width Linear Combinational Scan Vector Decompression,” Computer Aided Design, pp. 863 - 866, 2003. [Krishna 04] Krishna, C.V. and Touba, N.A., “3-stage Variable Length Continuous-flow Scan Vector Decompression Scheme,” VLSI Test Symposium, pp. 79-86, 2004. [Lee 99] Kuen-Jong Lee and Jih-Jeen Chen and Cheng-Hua Huang, “Broadcasting Test Patterns to Multiple Circuits,” Computer-Aided Design of Integrated Circuits and Systems, pp. 1793-1802, 1999. [Li 03] Li, L., and K. Chakrabarty, “Test Data Compression Using Dictionaries with Fixed-Length Indices,” Proc. of VLSI Test Symposium, pp. 219-224, 2003. [Li 05] Yu Te Liaw, and James C.-M. Li, “A Two-level Test Data Compression and Test Time Reduction Technique for SOC,” 16th VLSI/CAD Technical Program, 2005. [Lingappan 05] Lingappan, L., S. Ravi, A. Raghunathan, N. Jha, S. Chakaradhar, “Heterogeneous and Multi-level Compression Techniques for Test Volume Reduction in System-on-chip,” Proc., Int’l Conf. on VLSI Design, pp.187-193, 2005. [Mitra 03] Mitra, S., and K.S. Kim, “XMAX: X-tolerant Architectures for Maximal Test Compression,” Proc. of International Conference on Computer Design, pp. 326-330, 2003. [Rajski 02] Rajski, J., et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proc. of Int. Test Conf., pp. 301-310, 2002. [Rao 03] Rao, W., I. Bayraktaroglu, and A. Orailoglu, “Test Application Time and Volume Compression through Seed Overlapping,” Proc. of Design Automation Conference, pp. 732-737, 2003. [Reda 02] Reda, S., and A. Orailoglu, “Reducing Test Application Time through Test Data Mutation Encoding,” Proc. of Design, Automation, and Test in Europe, pp. 387-393, 2002. [Reddy 02] Reddy, S., K. Miyase, S. Kajihara, and I. Pomeranz, “On Test Data Volume Reduction for Multiple Scan Chain Designs,” Proc. of VLSI Test Symposium, pp. 103-108, 2002. [P1500] IEEE P1500 Standard for Embedded Core Test (SECT), IEEE Press, Piscataway, N.J., 2000; http://grouper.ieee.org/groups/1500/. [Samaranayake 02] S. Samaranayake, N. Sitchinava, R. Kapur M. B. Amin, and T. W. Williams, “Dynamic Scan: Driving Down the Cost of Test,” IEEE Computers, pp. 65-70, Oct., 2002. [Samaranayake 03] S. Samaranayake, and et. al., “A Reconfigurable Shared Scan-in Architecture,” Proc. IEEE VLSI Test Symp., pp. 9-14, 2003. [Touba 98] Jas, A. and Touba, N.A., “Test Vector Decompression via Cyclical Scan Chains and its Application to Testing Core-based Designs,” Test Conference, pp. 458-464, 1998. [Volkerink 02] Volkerink, E.H., A. Khoche, and S. Mitra, “Packet-based Input Test Data Compression Techniques,” Proc. of International Test Conference, pp. 154-163, 2002. [Volkerink 03] Volkerink, E.H., and S. Mitra, “Efficient Seed Utilization for Reseeding Based Compression,” Proc. of VLSI Test Symposium, pp. 232-237, 2003. [Wolff 02] Wolff, F.G., and C. Papachristou, “Multiscan-based Test Compression and Hardware Decompression Using LZ77,” Proc. of International Test Conference, pp. 331-339, 2002.; en-US; http://ntur.lib.ntu.edu.tw/handle/246246/57554; http://ntur.lib.ntu.edu.tw/bitstream/246246/57554/1/ntu-94-R92943110-1.pdf

الاتاحة: http://ntur.lib.ntu.edu.tw/handle/246246/57554
http://ntur.lib.ntu.edu.tw/bitstream/246246/57554/1/ntu-94-R92943110-1.pdf