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    المصدر: Journal of Atmospheric & Oceanic Technology; Feb2019, Vol. 36 Issue 2, p297-315, 19p, 5 Color Photographs, 1 Illustration, 8 Graphs, 1 Map

    مصطلحات موضوعية: OCEAN waves, TIDES, RADAR, VHF devices, INVERSE functions

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    المؤلفون: 林昆易, Lin, Kun-I

    المساهمون: 張慶元, Chang, Tsin-Yuan

    مصطلحات موضوعية: 鎖相迴路, Phase-Locked Loop

    Time: 45

    وصف الملف: 155 bytes; text/html

    Relation: [1] R. E. Best, Phase-Locked Loops Design, Simulation, and Applications, 3rd ed. New York: McGraw-Hill, 1997. [2] D. Rosemarine, “Accurately calculate PLL charge pump filter parameters,” Microwaves RF, pp. 89-94, Feb. 1999. [3] O. T. C. Chen, R. R. B. Sheen, “A power-efficient wide-range phase locked loop,” IEEE J. Solid State Circuits, vol. 37, pp. 51-62, Jan. 2002. [4] J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, “A wide-band width low-voltage PLL for PowerPC™ microprocessors,” IEEE J. Solid State Circuits, vol. 30, pp. 383-391, Apr. 1995. [5] P. Dudek, S. Szczepanski, and J.V. Hatfield, “A high-resolution CMOS time-to-digital converter utilizing a vernier delay line,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 240-247, Feb. 2000. [6] M. Tanaka, H. Ikeda, and S. Inaba, “Development of a monolithic time-to-amplitude converter for high precision TOF measurement,” IEEE Trans. Nucl. Sci., vol. 38, pp. 301-305. Apr. 1991. [7] J. C. Hsu, C. C. Su, “BIST for measuring clock jitter of Charge-Pump Phase- Locked Loops,” IEEE Transaction on Instrumentation and Measurement. vol. 57, pp. 276-285, Feb. 2008. [8] N. Abaskharoun, G. W. Roberts, “Circuits for on-chip sub-nanosecond signal capture and characterization,” IEEE Custom Integrated Circuits Conference. pp. 251–254, 2001. [9] A. H. Chan, G. W. Roberts, “A deep sub-micron timing measurement circuit using a single-stage Vernier delay line,” IEEE Custom Integrated Circuits Conference. pp. 77–80, 2002. [10] T. Xia, H. Zheng, J. Li, and A. Ginawi, “Self-refereed on-chip jitter measurement circuit using Vernier oscillators,” IEEE Computer Society Annual Symposium on VLSI, pp. 218-223, 2005. [11] K. Taylor, B. Nelson, A. Chong, H. Nguyen, H. Lin, M. Soma, H. Haggag, J. Huard, and J. Braag, “Experimental results for high-speed jitter measurement technique,” IEEE International Test Conference, pp. 85–94, 2004. [12] K. A. Jenkins, A. P. Jose, and D. F. Heidel, “An on-chip jitter measurement circuit with sub-picosecond resolution,” Europe Solid-State Circuits Conference, pp. 157–160, 2005. [13] S. Cherubal, A. Chatterjee, “A high-resolution jitter measurement technique using ADC sampling,” IEEE International Test Conference, pp. 838-847, 2001. [14] Nelson Soo, “Jitter measurement techniques,” Pericom Application Brief AB36, Nov.2000. [15] J.G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, Vol. 31, Iss. 11, pp. 1723-1732, Nov. 1996. [16] E. J. Hernandez, A. D. Sanchez, “Positive feedback CMOS charge-pump circuits for PLL applications,” IEEE 2001 Midwest Symposium Circuits and Systems, vol. 2, pp. 836-839, Aug. 2001. [17] L. Joonsuk, K. Beomsup, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE Journal of Solid-State Circuits, Vol. 35, Iss. 8, pp. 1137-1145, Aug. 2000. [18] M. H. Hu, “A digital control adaptive PLL with bandwidth control unit and jitter measurement BIST,” NTHU Master Thesis, pp. 22-30, Jul. 2007.; http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/32071