المؤلفون: I. Bietti, R. Tonietto, E. Zuffetti, CASTELLO, RINALDO

المساهمون: I., Bietti, R., Tonietto, E., Zuffetti, Castello, Rinaldo

مصطلحات موضوعية: CMOS INTEGRATED CIRCUITS, DIGITAL PHASE LOCKED LOOPS, FREQUENCY SYNTHESIZERS, PHASE NOISE, 0.13 MICRON, 12 PS, 15 MW, 2 GHZ, 3 MHZ, ADPLL TEST CHIP, CMOS PROCESS, ALL DIGITAL PLL RF SYNTHESIZER, ANALOG CIRCUITRY, DIGITAL CONTROL LOOP, LOW IN-BAND PHASE NOISE, LOW NOISE

وصف الملف: STAMPA

Relation: info:eu-repo/semantics/altIdentifier/isbn/9781424403035; ispartofbook:Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European; Solid-State Circuits Conference, ESSCIRC 2006; firstpage:150; lastpage:153; http://hdl.handle.net/11571/30090

الاتاحة: http://hdl.handle.net/11571/30090