المؤلفون: Duric, Milovan, Palomar Pérez, Óscar, Smith, Aaron, Stanic, Milan, Unsal, Osman Sabri, Cristal Kestelman, Adrián, Valero Cortés, Mateo, Burger, Doug, Veidenbaum, Alexander V

المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions

مصطلحات موضوعية: Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Microprocessors, Computer architecture, DLP accelerator, DVX enabled 4-core EDGE CMP, EDGE architecture, Cost-effective technique, Data parallel workloads, Dedicated accelerator, Dynamic vector execution, Energy efficient substrate, Energy-delay product, Explicit data graph execution, Functionality, General purpose CMP, General purpose EDGE chip, Multiprocessor, High performance vector design, Low power chip multiprocessor, Minimal hardware, Modest processor, Special-purpose vector architecture, Vector accelerator, Vector control, Vector processor, Microprocessor chips, Multiprocessing systems, Computational modeling, Hardware

وصف الملف: 8 p.

Relation: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6893190; info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL; Duric, M. [et al.]. Dynamic-vector execution on a general purpose EDGE chip multiprocessor. A: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. "International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIV): proceedings: July 14-17, 2014: Samos, Greece". Samos: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 18-25.; http://hdl.handle.net/2117/27788

الاتاحة: http://hdl.handle.net/2117/27788
https://doi.org/10.1109/SAMOS.2014.6893190

المؤلفون: Osman Unsal, Doug Burger, Alexander V. Veidenbaum, Adrian Cristal, Oscar Palomar, Aaron L. Smith, Milovan Duric, Mateo Valero, Milan Stanic

المساهمون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions

المصدر: ICSAMOS
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
Universitat Jaume I

مصطلحات موضوعية: DVX enabled 4-core EDGE CMP, Speedup, Computer science, Explicit data graph execution, Parallel computing, Instruction set, Energy efficient substrate, Dynamic vector execution, Functionality, General purpose CMP, Vector control, General purpose EDGE chip, Microprocessor chips, Dedicated accelerator, Message systems, 1. No poverty, Registers, Computational modeling, Special-purpose vector architecture, EDGE architecture, Vectors, Chip, Arquitectura d'ordinadors, Enginyeria electrònica::Microelectrònica [Àrees temàtiques de la UPC], Vector processor, High performance vector design, Multiprocessor, Enhanced Data Rates for GSM Evolution, Low power chip multiprocessor, Efficient energy use, Multiprocessing, Data parallel workloads, Cost-effective technique, Instruction sets, Hardware, Energy-delay product, Modest processor, Computer architecture, Microprocessors, Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], Multiprocessing systems, business.industry, DLP accelerator, Vector accelerator, Embedded system, Microprocessadors, Minimal hardware, business

وصف الملف: application/pdf

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::65626af2bd51d5ffc4980c6882176d10
https://doi.org/10.1109/samos.2014.6893190

المؤلفون: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions, Duric, Milovan, Palomar Pérez, Óscar, Smith, Aaron, Stanic, Milan, Unsal, Osman Sabri, Cristal Kestelman, Adrián, Valero Cortés, Mateo, Burger, Doug, Veidenbaum, Alexander V

مصطلحات الفهرس: Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Microprocessors, Computer architecture, DLP accelerator, DVX enabled 4-core EDGE CMP, EDGE architecture, Cost-effective technique, Data parallel workloads, Dedicated accelerator, Dynamic vector execution, Energy efficient substrate, Energy-delay product, Explicit data graph execution, Functionality, General purpose CMP, General purpose EDGE chip, Multiprocessor, High performance vector design, Low power chip multiprocessor, Minimal hardware, Modest processor, Special-purpose vector architecture, Vector accelerator, Vector control, Vector processor, Microprocessor chips, Multiprocessing systems, Computational modeling, Hardware, Instruction sets, Message systems, Registers, Vectors, Microprocessadors, Arquitectura d'ordinadors, Conference report

URL: http://hdl.handle.net/2117/27788
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6893190
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6893190
info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL