المؤلفون: 설정우

المساهمون: 정덕균, Jung-Woo Sull, 공과대학 전기·정보공학부

مصطلحات موضوعية: coprime, digitally controlled delay line (DCDL), digital delay-locked loop (DLL), duty-cycle corrector (DCC), multiplexer (MUX), octa-phase error corrector (OEC), 621.3

وصف الملف: xii, 114

Relation: 000000177636; https://hdl.handle.net/10371/196416; https://dcollection.snu.ac.kr/common/orgView/000000177636; I804:11032-000000177636; 000000000050▲000000000058▲000000177636▲

الاتاحة: https://hdl.handle.net/10371/196416
https://dcollection.snu.ac.kr/common/orgView/000000177636

المؤلفون: M.Indu*, S.HasmashruthiA.Nandhini, N.Megala

المصدر: INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY, 5(4), 117-122, (2016-04-05)

مصطلحات موضوعية: ALL Digital circuit, glitching, DCDL

Relation: https://doi.org/; https://doi.org/10.5281/zenodo.48842; oai:zenodo.org:48842

الاتاحة: https://doi.org/10.5281/zenodo.48842

المؤلفون: Ho, Y.-H, Yao, C.-Y.

مصطلحات موضوعية: All-digital delay-locked loop (ADDLL), deskew buffer, digital-controlled delay line (DCDL), successive-approximation register (SAR), synchronization

وصف الملف: 210 bytes; text/html

Relation: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 24, Issue 2, Page: 759 - 763; http://ir.lib.ntust.edu.tw/handle/987654321/66409; http://ir.lib.ntust.edu.tw/bitstream/987654321/66409/1/index.html

الاتاحة: http://ir.lib.ntust.edu.tw/handle/987654321/66409
https://doi.org/10.1109/TVLSI.2015.2407577
http://ir.lib.ntust.edu.tw/bitstream/987654321/66409/1/index.html

المؤلفون: Elmallah, Ahmed Safwat Mohamed Aboelenein

المساهمون: Hanumolu, Pavan Kumar, Rosenbaum, Elyse, Schutt-Aine, Jose E., Dragic, Peter D.

مصطلحات موضوعية: DTC, PLL, TDC, Fractional-N, DCDL, INL, Noise cancellation, Frequency synthesizer, Phase-locked loop, Delay-locked loop, Time to digital converter

وصف الملف: application/pdf

Relation: http://hdl.handle.net/2142/108294

الاتاحة: http://hdl.handle.net/2142/108294

المؤلفون: R. Giordano, F. Ameli, P. Bifulco, V. Bocci, S. Cadeddu, V. Izzo, A. Lai, A. Aloisio

المساهمون: Giordano, R., Ameli, F., Bifulco, P., Bocci, V., Cadeddu, S., Izzo, V., Lai, A., Aloisio, A.

مصطلحات موضوعية: Data acquisition, Delay line, Digital system, Field programmable gate array, Digitally-controlled delay line (DCDL), FPGA

Relation: info:eu-repo/semantics/altIdentifier/wos/WOS:000372013500009; volume:62; issue:6; firstpage:3163; lastpage:3171; numberofpages:9; journal:IEEE TRANSACTIONS ON NUCLEAR SCIENCE; http://hdl.handle.net/11588/667853; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-84961838384

الاتاحة: http://hdl.handle.net/11588/667853
https://doi.org/10.1109/TNS.2015.2497539

المؤلفون: Vincenzo Izzo, R. Giordano, Adriano Lai, S. Mastroianni, V. Bocci, P. Bifulco, Fabrizio Ameli, S. Cadeddu, Alberto Aloisio

المساهمون: Giordano, R., Ameli, F., Bifulco, P., Bocci, V., Cadeddu, S., Izzo, V., Lai, A., Aloisio, A.

مصطلحات موضوعية: Nuclear and High Energy Physics, Distributed database, business.industry, Computer science, Hardware description language, Field programmable gate array, Data acquisition, Delay line, Nuclear Energy and Engineering, Scalability, Electronic engineering, Digitally-controlled delay line (DCDL), Digital system, Place and route, Electrical and Electronic Engineering, business, Field-programmable gate array, computer, Computer hardware, FPGA, computer.programming_language, Block (data storage), Group delay and phase delay

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8689fbd2b61e8176a290aa47c27e1105
http://hdl.handle.net/11588/667853

المؤلفون: Chung, CC, Lee, CY

المساهمون: 電子工程學系及電子研究所, Department of Electronics Engineering and Institute of Electronics

مصطلحات موضوعية: delay-locked loops (DLLs), digitally controlled delay line (DCDL), multiphase clock generation, phase synchronization

Relation: http://dx.doi.org/10.1109/JSSC.2003.822890; http://hdl.handle.net/11536/26981; IEEE JOURNAL OF SOLID-STATE CIRCUITS

الاتاحة: http://hdl.handle.net/11536/26981
https://doi.org/10.1109/JSSC.2003.822890

المؤلفون: Yao, C.-Y., Ho, Y.-H., Chiu, Y.-Y., Yang, R.-J.

مصطلحات موضوعية: All digital delay-locked loop (ADDLL), clock synchronization, de-skew buffer, digitally controlled delay line (DCDL), successive-approximation-register (SAR) controller

Relation: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 23, Issue 3, Page: 567 - 574; http://ir.lib.ntust.edu.tw/handle/987654321/51537; http://ir.lib.ntust.edu.tw/bitstream/987654321/51537/-1/index.html

الاتاحة: http://ir.lib.ntust.edu.tw/handle/987654321/51537
https://doi.org/10.1109/TVLSI.2014.2313131
http://ir.lib.ntust.edu.tw/bitstream/987654321/51537/-1/index.html

المؤلفون: 鍾登皓

مصطلحات موضوعية: 延遲鎖定迴路, 二元搜索法, 遞迴二元搜索法, 延遲線, 動態頻率調整, ADDLL, DLL, SAR, RSAR, FVSAR, DCDL, DVFS, Over clock, LDSAR

وصف الملف: 143 bytes; text/html

Relation: http://ir.lib.ntust.edu.tw/handle/987654321/16131; http://ir.lib.ntust.edu.tw/bitstream/987654321/16131/1/index.html

الاتاحة: http://ir.lib.ntust.edu.tw/handle/987654321/16131
http://ir.lib.ntust.edu.tw/bitstream/987654321/16131/1/index.html