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1Academic Journal
المؤلفون: Antonov, Yury, Tikka, Tero, Stadius, Kari, Ryynänen, Jussi
المساهمون: Department of Micro and Nanosciences, Aalto-yliopisto, Aalto University
مصطلحات موضوعية: CMOS digital integrated circuits, calibration, digital phase locked loops, optimisation, ADPLL phase accumulator speed optimization, CMOS, MIPI M-PHY serial link transmitter, PVT calibration, all-digital phase-locked loop, clock generator, frequency 1.2 GHz to 5.8 GHz, loop type changing criteria, phase digitization process, power saving, size 40 nm, CMOS integrated circuits, Clocks, Delays, Monitoring, Phase locked loops, Pipeline processing, Transmitters
وصف الملف: application/pdf
Relation: European Conference on Circuit Theory and Design; 2015 European Conference on Circuit Theory and Design, ECCTD 2015; Antonov , Y , Tikka , T , Stadius , K & Ryynänen , J 2015 , All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter . in 2015 European Conference on Circuit Theory and Design, ECCTD 2015 . , 7300035 , IEEE , European Conference on Circuit Theory and Design , Trondheim , Norway , 24/08/2015 . https://doi.org/10.1109/ECCTD.2015.7300035; PURE UUID: 277a0097-e13b-4bc3-bc2d-4ec67be00f40; PURE ITEMURL: https://research.aalto.fi/en/publications/277a0097-e13b-4bc3-bc2d-4ec67be00f40; PURE LINK: http://www.scopus.com/inward/record.url?scp=84959513462&partnerID=8YFLogxK; PURE FILEURL: https://research.aalto.fi/files/80695336/Antonov_All_Digital_Phase_Locked_IEEE.pdf; https://aaltodoc.aalto.fi/handle/123456789/113379; URN:NBN:fi:aalto-202203162258
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المؤلفون: Tero Tikka, Jussi Ryynanen, Yury Antonov, Kari Stadius
المساهمون: Department of Micro and Nanosciences, Aalto-yliopisto, Aalto University
المصدر: ECCTD
مصطلحات موضوعية: Engineering, PVT calibration, Monitoring, optimisation, Serial communication, Phase (waves), Phase locked loops, power saving, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Clock generator, Delays, ADPLL phase accumulator speed optimization, Clocks, all-digital phase-locked loop, business.industry, clock generator, CMOS, loop type changing criteria, Transmitter, phase digitization process, CMOS digital integrated circuits, calibration, CMOS integrated circuits, Transmitters, digital phase locked loops, size 40 nm, Phase-locked loop, Loop (topology), MIPI M-PHY serial link transmitter, Pipeline processing, Accumulator (computing), business, frequency 1.2 GHz to 5.8 GHz
وصف الملف: application/pdf