المؤلفون: 廖育德, Liao, Yu-De

المساهمون: 王行健, 中興大學, 王朝欽, 李淑敏, 陳繼展

مصطلحات موضوعية: Ring Generator, 可測試度設計, Design-For-Testability, Scan Cells Partitioning, 掃描細胞分割, 線性迴授位移暫存器

Relation: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-3007201015382500; U0005-3007201015382500; http://hdl.handle.net/11455/19748

الاتاحة: http://hdl.handle.net/11455/19748

المؤلفون: 陳森龍, Sel-Lung Chen

المساهمون: 劉靖家, Jing-Jia Liou

مصطلحات موضوعية: 內建式自我測試, 延遲錯誤, 線性迴授移位暫存器, 傳輸延遲錯誤, 測試, BIST, Delay fault, LFSR, Transition delay fault, Testing

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وصف الملف: 155 bytes; text/html

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Test Conf. (ITC), pp. 1120–1129, Oct. 2002. [15] K.-T.Cheng, “Test generation for delay faults in non-scan and partial scan sequential circuits,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), pp. 554–559, Nov. 1992. [16] I. Pomeranz and S.M.Reddy, “Generalization of independemt faults for transition faults,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 7–12, Apr. 1992. [17] I. P. Y. Shao and S.M.Reddy, “On generating high quality tests for transition fauls,” in IEEE Asian Test Symp. (ATS), pp. 1–8, Nov. 2002. [18] S. B.Seshadri, I.Pomeranz and S.Kundu, “Path-oriented transition fault test generation considering operating conditions,” in Proc. European Test Symposium(ETS), pp. 54–59, May 2005. [19] M. Abadir and J.Zhu, “Transition test generation using replicate-and-reduce transform for scan-based designs,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 22–27, May 2003. [20] X. S.Chakravarty, P.J. Thadikaran and M. Hsiao, “Novel atpg algorithm for transition faults,” in Proc. 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European Design and Test Conference, pp. 69–76, 1997. [51] B. Cockburn and A.-C. Kwong, “Transition maximization techniques for enhancing the twopattern fault coverage of pseudorandom test pattern generators,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 26–30, 1998. [52] J. Savir, “At-speed test in not necessarily an ac test,” in Proc. Int. Test Conf. (ITC), pp. 722– 728, 1991. [53] S.Cremoux, C.Fagot, P.Girard, C.Landraut, and S.Pravossoudovitch, “A new test pattern generation method for delay fault testing,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 296–301, Apr. 1996. [54] H. H. M. Keim, I. Polian and B. Becker, “A scalable bist architecture for delay faults,” in Proc. IEEE European Test Workship (ETW), pp. 14–15, 1999. [55] D. N. Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A versatile built-in self test scheme for delay fault testing,” in Proc. Design, Automation and Test in Europe (DATE), p. 756, 2000. [56] I. P. H. Lee and S. Reddy, “Scan bist targeting transition faults using a markov source,” in Proc. IEEE Quality Electronic Design, pp. 497–502, 2004. [57] F. L. Y.C Lin and K. Cheng, “Pseudo-functional scan-based bist for delay fault,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 229–234, May 2005. [58] S. R.Srinivasan andM.A.Breuer, “Novel test pattern generator for pseudo-exhaustive testing,” in Proc. Int. Test Conf. (ITC), pp. 1041–1050, Oct. 1993. [59] N. P.Kitsos, N.Sklavos and O.Koufopavlou, “A reconfigurable linear feedback shift register (lfsr) for the bluetooth system,” in Proceedings of IEEE International Conference on Electronics, Circuits and Systems, pp. 991–994, Sept. 2001. [60] C.-H. Wu, “A satisfiability-based atpg for path delay faults,” Master’s thesis, National Tsing Hua University, Dept. Electrical Engineering, July 2005.; http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/31217

الاتاحة: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/31217

المؤلفون: 陳森龍, Sel-Lung Chen

المساهمون: 劉靖家, Jing-Jia Liou

مصطلحات موضوعية: 內建式自我測試, 延遲錯誤, 線性迴授移位暫存器, 傳輸延遲錯誤, 測試, BIST, Delay fault, LFSR, Transition delay fault, Testing

Time: 45

وصف الملف: 1400832 bytes; application/octet-stream

Relation: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/7876

الاتاحة: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/7876