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1Dissertation/ Thesis
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3Dissertation/ Thesis
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4Dissertation/ Thesis
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5Dissertation/ Thesis
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7Dissertation/ ThesisApplication and implementation of monolithic microwave integated circuits with CMOS active inductors
المؤلفون: Yu-Te Liao, 廖育德
Thesis Advisors: Liang-Hung Lu, 呂良鴻
وصف الملف: 71
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8Dissertation/ Thesis
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9Dissertation/ Thesis
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10Dissertation/ Thesis
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11Report
المؤلفون: 蔡宜佑(Yi-Yu Tsai), 邱俊誠(Jin-Chern Chiou), 歐陽盟, 廖育德, 劉美均, 江鈞綺(Chun-Chi Chiang), 陳幸宜(Hsin-Yi Chen), 段正仁(Jeng-Ren Duann)
المساهمون: 醫學院醫學系學士班眼科學科, 中國附醫眼科部
Relation: http://ir.cmu.edu.tw/ir/handle/310903500/53200; http://ir.cmu.edu.tw/ir/bitstream/310903500/53200/-1/index.html
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12
المساهمون: 行銷與流通管理系
Time: 4
وصف الملف: 1961680 bytes; application/pdf
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13Dissertation/ Thesis
المؤلفون: 廖育德, Yu-De Liao
المساهمون: 土木工程學系所, 林炳森
مصطلحات موضوعية: Reused Water；Femwater；Paddy Field, 回歸水；水收支平衡法；Femwater程式模擬
Relation: U0005-2811201416184333; http://hdl.handle.net/11455/90954
الاتاحة: http://hdl.handle.net/11455/90954
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14Dissertation/ Thesis
المؤلفون: 廖育德, Liao, Yu-De
المساهمون: 王行健, 中興大學, 王朝欽, 李淑敏, 陳繼展
مصطلحات موضوعية: Ring Generator, 可測試度設計, Design-For-Testability, Scan Cells Partitioning, 掃描細胞分割, 線性迴授位移暫存器
Relation: http://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-3007201015382500; U0005-3007201015382500; http://hdl.handle.net/11455/19748
الاتاحة: http://hdl.handle.net/11455/19748
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15Dissertation/ Thesis
المؤلفون: 廖育德, Liao, Yu-Te
المساهمون: 都市計劃學系碩博士班, 姜渝生, Chiang, Yu-Sheng
مصطلحات موضوعية: event history analysis, first investment, investment decision, dynamics, 首次投資, 動態, 投資決策, 事件史分析法, manag, eco
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16Dissertation/ Thesis
المؤلفون: 廖育德, Liaw, Yu-Te
المساهمون: 李建模, 臺灣大學：電子工程學研究所
مصطلحات موضوعية: 測試資料壓縮, 測試時間壓縮, 系統晶片測試整合, Test data compression, Test time compression, SoC test integration
وصف الملف: 600537 bytes; application/pdf
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[Chandra 03] Chandra, A. and Chakrabarty, K., “Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-length (FDR) Codes,” IEEE Transactions on Computers, Volume: 52, Issue: 8, pp. 1076-1088, 2003. [Das 00] Das, D., and N.A. Touba, “Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns,” Proc. of International Test Conference, pp. 115-122, 2000. [Hamzaoglu 99] Hamzaoglu, I., and J.H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” Proc. of Int. Symposium on Fault Tolerant Computing, pp. 260-267, 1999. [Hellebrand 95a] Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” IEEE Trans. on Computers, Vol. 44, No. 2, pp. 223-233, 1995. [Hellebrand 95b] Hellebrand, S., B. Reeb, S. Tarnick, and H.-J. Wunderlich, “ Pattern Generation for a Deterministic BIST Scheme,” Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 88-94, 1995. [Hsu 01] Hsu, F.F. and Butler, K.M. and Patel, J.H., “A Case Study on the Implementation of the Illinois Scan Architecture,” Test Conference, pp. 538-547, 2001. [Huffman 52] D. A. Huffman, “A Method for the Construction of Minimum Redundancy Codes,” in Proc. IRE, vol. 40, 1952, pp. 1098–1101. [Ichihara 00] Ichihara, H., Kinoshita, K., Pomeranz, I. and Reddy, S.M., “Test Transformation to Improve Compaction by Statistical Encoding,” VLSI Design, pp. 294-299, 2000. [Jas 98] Jas, A. and Touba, N.A., “Test Vector Decompression via Cyclical Scan Chains and its Application to Testing Core-based Designs,” Test Conference, pp. 458-464, 1998. [Jas 99] Jas, A., J. Ghosh-Dastidar, and N.A. Touba, “Scan Vector Compression/Decompression Using Statistical Coding,” Proc. of IEEE VLSI Test Symposium, pp. 114-120, 1999. [Jas 00] Jas, A., B. Pouya, and N.A. Touba, “Virtual Scan Chains: A Means for Reducing Scan Length in Cores,” Proc. of VLSI Test Symposium, pp. 73-78, 2000. [Konemann 91] Konemann, B., “LFSR-Coded Test Patterns for Scan Designs,” Proc. of European Test Conf., pp. 237-242, 1991. [Konemann 01] Konemann, B., “A SmartBIST Variant with Guaranteed Encoding,” Proc. of Asian Test Symposium, pp. 325-330, 2001. [Krishna 01] Krishna, C.V., A. Jas, and N.A. Touba, “Test Vector Encoding Using Partial LFSR Reseeding,” Proc. of IEEE International Test Conference, pp. 885-893, 2001. [Krishna 02] Krishna, C.V., and N.A. Touba, “Reducing Test Data Volume Using LFSR Reseeding with Seed Compression,” Proc. of IEEE International Test Conference, pp. 321-330, 2001. [Krishna 03] Krishna, C.V. and Touba, N.A., “Adjustable Width Linear Combinational Scan Vector Decompression,” Computer Aided Design, pp. 863 - 866, 2003. [Krishna 04] Krishna, C.V. and Touba, N.A., “3-stage Variable Length Continuous-flow Scan Vector Decompression Scheme,” VLSI Test Symposium, pp. 79-86, 2004. [Lee 99] Kuen-Jong Lee and Jih-Jeen Chen and Cheng-Hua Huang, “Broadcasting Test Patterns to Multiple Circuits,” Computer-Aided Design of Integrated Circuits and Systems, pp. 1793-1802, 1999. [Li 03] Li, L., and K. Chakrabarty, “Test Data Compression Using Dictionaries with Fixed-Length Indices,” Proc. of VLSI Test Symposium, pp. 219-224, 2003. [Li 05] Yu Te Liaw, and James C.-M. Li, “A Two-level Test Data Compression and Test Time Reduction Technique for SOC,” 16th VLSI/CAD Technical Program, 2005. [Lingappan 05] Lingappan, L., S. Ravi, A. Raghunathan, N. Jha, S. Chakaradhar, “Heterogeneous and Multi-level Compression Techniques for Test Volume Reduction in System-on-chip,” Proc., Int’l Conf. on VLSI Design, pp.187-193, 2005. [Mitra 03] Mitra, S., and K.S. Kim, “XMAX: X-tolerant Architectures for Maximal Test Compression,” Proc. of International Conference on Computer Design, pp. 326-330, 2003. [Rajski 02] Rajski, J., et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proc. of Int. Test Conf., pp. 301-310, 2002. [Rao 03] Rao, W., I. Bayraktaroglu, and A. Orailoglu, “Test Application Time and Volume Compression through Seed Overlapping,” Proc. of Design Automation Conference, pp. 732-737, 2003. [Reda 02] Reda, S., and A. Orailoglu, “Reducing Test Application Time through Test Data Mutation Encoding,” Proc. of Design, Automation, and Test in Europe, pp. 387-393, 2002. [Reddy 02] Reddy, S., K. Miyase, S. Kajihara, and I. Pomeranz, “On Test Data Volume Reduction for Multiple Scan Chain Designs,” Proc. of VLSI Test Symposium, pp. 103-108, 2002. [P1500] IEEE P1500 Standard for Embedded Core Test (SECT), IEEE Press, Piscataway, N.J., 2000; http://grouper.ieee.org/groups/1500/. [Samaranayake 02] S. Samaranayake, N. Sitchinava, R. Kapur M. B. Amin, and T. W. Williams, “Dynamic Scan: Driving Down the Cost of Test,” IEEE Computers, pp. 65-70, Oct., 2002. [Samaranayake 03] S. Samaranayake, and et. al., “A Reconfigurable Shared Scan-in Architecture,” Proc. IEEE VLSI Test Symp., pp. 9-14, 2003. [Touba 98] Jas, A. and Touba, N.A., “Test Vector Decompression via Cyclical Scan Chains and its Application to Testing Core-based Designs,” Test Conference, pp. 458-464, 1998. [Volkerink 02] Volkerink, E.H., A. Khoche, and S. Mitra, “Packet-based Input Test Data Compression Techniques,” Proc. of International Test Conference, pp. 154-163, 2002. [Volkerink 03] Volkerink, E.H., and S. Mitra, “Efficient Seed Utilization for Reseeding Based Compression,” Proc. of VLSI Test Symposium, pp. 232-237, 2003. [Wolff 02] Wolff, F.G., and C. Papachristou, “Multiscan-based Test Compression and Hardware Decompression Using LZ77,” Proc. of International Test Conference, pp. 331-339, 2002.; en-US; http://ntur.lib.ntu.edu.tw/handle/246246/57554; http://ntur.lib.ntu.edu.tw/bitstream/246246/57554/1/ntu-94-R92943110-1.pdf
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17Dissertation/ Thesis
المؤلفون: 廖育德, Liao, Yu-Te
المساهمون: 呂良鴻, 臺灣大學：電子工程學研究所
مصطلحات موضوعية: 主動電感, 偶合器, 分波器, 極小化, active inductor, phase shifter, wilkinson power divider, hybrid
Relation: [1] J. R. Long and M. A. Copeland, “The modeling, characterization, and design of monolithic inductors for silicon RF ICs,” IEEE J. Solid-State Circuits, vol. 32, pp. 357–369, Mar. 1997. [2] H. G. Booker, Energy in Electromagnetism, London, New York: Peter Peregrinus on behalf of the Institution of Electrical Engineers, 1982. [3] C.P. Yue, S.S. Wong,” On-chip spiral inductors with patterned ground shields for Si-based RF ICs,” IEEE J. Solid-State Circuits, Vol. 33, no. 5, pp. 743-752, May, 1998. [4] J.M. Lopez-Villegas, J. Samitier, C. Cane, P. Losantos, J. Bausells,” Improvement of the quality factor of RF integrated inductors by layout optimization” IEEE Trans. Microwave Theory and Techniques, vol. 48, no. 1, pp. 76-83, Jan., 2000. [5] Chih-Chun Tang, Chia-Hsin Wu, Shen-Iuan Liu,” Miniature 3-D Inductors in Standard CMOS Process,” IEEE J. Solid-State Circuits, Vol. 37, no. 4, pp. 471-480, April, 2002. [6] Y. Yoshihara, H. Sugawara, H. Ito, K. Okada, K.Masu,” A wide tuning range CMOS VCO using variable inductor,” in IEEE Silicon Monolithic Integrated Circuits in RF Systems, MI, pp. 278–281, Sept. 2004 [7] W.H. Holmes, W.E.Heinlein, S. Grutzmann,” Sharp-cutoff low-pass filters using floating gyrators,” IEEE J. Solid-State Circuits, Vol. 4, no. 1, pp. 38-50, Feb., 1969. [8] U. Yodprasit and J. Ngarmnil, “Q-enhancing technique for RF CMOS active inductor”, IEEE Int. Symp. on Circuits and Systems, 2000, pp. 589-592. [9] Yue Wu, M. Ismail, H. Olsson,” A novel CMOS fully differential inductorless RF bandpass filter,” IEEE Int. Symp. on Circuits and Systems, 2000, pp. 149-152. [10] A. Thanachayanont and A. Payne, “VHF CMOS integrated active inductor,” Electron. Lett., vol. 32, pp. 999–1000, May 1996. [11] Chao-Chih Hsiao, Chin-Wei Kuo, Chien-Chih Ho, and Yi-Jen Chan,“Improved quality-factor of 0.18μm CMOS active inductor by a feedback resistance design,”IEEE Microwave and Wireless Components Lett., vol. 12, pp. 467-469, Dec. 2002. [12] K. Miyaguchi, M. Hieda, K. Nakahara, H. Kurusu, M. Nii, M. Kasahara, T. Takagi, and S. Urasaki,”An ultra-broad-band reflection-type phase-shifter MMIC with series and parallel LC circuits,” IEEE Trans. Microwave Theory and Techniques, vol. 49, no. 12, pp. 2446-2452, Dec. 2001. [13] A. S. Nagra, and R. A. York, “Distributed analog phase shifters with low insertion loss,” IEEE Trans. Microwave Theory and Techniques, vol. 47, no. 9, pp. 1705-1711, Sept. 1999. [14] P.-Y. Chen, T.-W. Huang, H. Wang, Y.-C. Wang, C.-H. Chen, and P.-C. Chao, “K-band HBT and HEMT monolithic active phase shifters using vector sum method,” IEEE Trans. Microwave Theory and Techniques, vol. 52, no. 5, pp. 1414-1424, May 2004. [15] D. Viveiros, Jr., D. Consonni, and A. K. Jastrzebski, “A tunable all-pass MMIC active phase shifter,”IEEE Trans. Microwave Theory and Techniques, vol. 50, no. 8, pp. 1885-1889, Aug. 2002. [16] H.Zarei, D.J. Allstot, “A low-loss phase shifter in 180 nm CMOS for multiple-antenna receivers,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2004, pp. 392-534. [17] H. Hayashi, M. Muraguchi, Y. Umeda, T. Enoki, ”A high-Q broad-band active inductor and its application to a low-loss analog phase shifter,” IEEE Trans. Microwave Theory and Techniques, vol. 44, no. 12, pp. 2369-2374, Dec. 1996. [18] M. Rodwell, M. Kamegawa, R. Yu, M. Case, E. Carman, K.S. Giboney, “GaAs nonlinear transmission lines for picosecond pulse generation and millimeter-wave sampling” IEEE Trans. Microwave Theory and Techniques, vol. 39, pp. 1194-1204, July 1991. [19] S. Hamedi-Hagh, C. Salama, “CMOS wireless phase-shifted transmitter,” IEEE J. Solid-State Circuits, vol. 39, pp. 1242-1252, Aug. 2004. [20] F. Ellinger, R. Vogt, and W. Bachtold, “Ultra compact, low loss, varactor tuned phase shifter MMIC at C-band,” IEEE Microwave and Wireless Components Letters, vol. 11, no. 3, pp. 104-105, March 2001. [21] D. Pozar, “Microwave Engineering”, second Edition. [22] K. Nishikawa, T. Tokumitsu, and I. Toyoda,“Miniaturized Wilkinson power divider using three-dimensional MMIC technology”, IEEE Microwave and Guided Wave Letters, vol. 6, no. 10, pp.372-374, Oct. 1996. [23] C. Ng, M. Chongcheawchamnan, and I. Robertson,“Lumped distributed hybrids in 3D-MMIC technology,” IEE Proc., Microwaves, Antennas and Propagation, vol. 151, pp. 370-374, Aug. 2004. [24] M. C. Scardelletti, G. E. Ponchak, and T. M. Weller, “Miniaturized Wilkinson power dividers utilizing capacitive loading”, IEEE Microwave and Wireless Components Letters, vol. 12, no. 1, pp.6-8, Jan. 2002. [25] Hsin-Chia Lu and Tah-Hsiung Chu,”Multiport scattering matrix measurement using a reduced-port network analyzer,”IEEE Trans. Microwave Theory and Techniques, vol. 51,no. 5, pp. 1525-1533, May 2003. [26] C. Seguinot, P. Kennis, J.-F Legier, F. Huret, E. Paleczny, L. Hayden,” Multimode TRL. A new concept in microwave measurements: theory and experimental verification,” IEEE Trans. Microwave Theory and Techniques, vol. 46, no. 5, pp. 536-542, May 1998.; en-US; http://ntur.lib.ntu.edu.tw/handle/246246/57313